IC-TW2 Datasheet, PDF (29/30 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
PCB LAYOUT GUIDELINES
Rev D3, Page 29/30
The iC-TW2 is a noise sensitive mixed signal device,
which requires careful PCB layout considerations. Vi-
olating the layout guidelines can result in poor perfor-
mance. Please consider Figure 22 .
Power pins VDDA (pin 10) and VDD (pin 1) must be
decoupled with 1 µF.
Trace length to VDD pins must be no longer than 3 mm.
The decoupling caps can be placed on the bottom side
of the PCB directly connecting it to the iC-TW2 pads
using vias.
Ground pins GND (pin 6) and GNDA (pin 11) must be
tied to the center exposed pad.
The exposed pad is then directly connected to the PCB
ground plane using several vias.
VSS pin 6 and 11 tied to exposed
pad. EP strapped to ground plane
using several vias .
1 µF C603
1 µF C603
Max 3 mm from VDD pin 1 and 10
to 1 µF decoupling caps.
Figure 22: PCB layout guidelines
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