IC-TW2 Datasheet, PDF (23/30 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
SCLK
Rev D3, Page 23/30
SDAT
0
0 ^{a4 a3 a2 a1 a0 d7 d6}
d1 d0
0
01
SDAT is sampled on
falling edge of SCLK
00 indicates write
5 bit address
8 bit data
SDAT is externally driven
extra clocks before
new access new access
Figure 13: Register bank write access on 2W-Interface
On a register read access the register content is
shifted out on SDAT. A read access is indicated by
SDAT 10 after the start bit. There is an idle clock re-
quired between the last address bit a(0) and the first
data bit d(7) returned on SDAT. This clock cycle is used
to avoid any bus contention while turning around the
bus driver.
SCLK
SDAT
1
0 ^{a4 a3 a2 a1 a0}
d7 d6
d0
0
01
SDAT is sampled on
falling edge of SCLK
10 indicates read
5 bit address
8 bit data
SDAT is externally driven
SDAT is driven by iC-TW2
extra clocks before
new access new access
Figure 14: Register bank read access on 2-wire interface
Write access to the EEPROM follows the procedure
depicted in Figure 15. A start bit is followed by four
command bits c-1-e-b. The encoding of the command
bits is shown in Table 31. The most useful command
is 0100 which performs an erase followed by a write
therefore allowing the user to write a new value to the
EEPROM with only one interface access.
SCLK
SDAT
c
1
e
b a2 a1 a0 d31 d30
d1 d0
SDAT is sampled on
falling edge of SCLK
3 bit address
SDAT is externally driven
command select erase control block operation
32 bit data
extra clocks before
new access
Figure 15: EEPROM write access on 2-wire interface
0
0
1
20
ms
wait for at least 20ms
before any new access