IC-TW2 Datasheet, PDF (24/30 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
SCLK
Rev D3, Page 24/30
SDAT
1
1
0
0 a2 a1 a0
d31 d30
d0
0
0
1
SDAT is sampled on
falling edge of SCLK
3 bit address
SDAT is driven externally
32 bit data
SDAT is driven by iC-TW2
extra clocks before
new access
new access
Figure 16: EEPROM read access on 2-wire interface
The 3 bit address a(2:0) selects the EEPROM register
to write to (Figure 12). Each EEPROM register is 32
bits wide, therefore 32 data bits d(31:0) are sent across
the interface. At least 20 ms delay is required after ev-
ery transaction before any new access can start.
EEPROM read access is shown in Figure 16. The start
bit is followed with the 4 bit read command 1100 and
the 3 bit address a(2:0). An idle clock cycle is used
to avoid any contention on SDAT while reversing data
flow direction. Finally d(31:0) is shifted out on SDAT.
EEPROM read access is slow. Please take notice of
the timings in Table 32.
At least one extra clock with SDAT low is required after
every transaction on the 2-wire interface before a new
access is started. The interface will not work correctly
if this clock cycle is omitted.
EEPROM Commands
c 1 e b Description
0 1 0 0 Erase followed by write
0 1 0 1 Block erase followed by block write
0 1 1 0 Block write
0 1 1 1 Read. Please refer to Figure 16 for more details
1 1 0 1 Reserved. Do not use this command
1 1 1 0 Erase
1 1 1 1 Block erase
Purpose
Normal EEPROM programming
Test only
Test only
Special production environment
Table 31: EEPROM Commands
2W-Interface timing
The timing of the 2W-Interface is dependent on the
type of access performed. Register bank access and
EEPROM write access can be performed at full speed.
EEPROM read access requires a slow SCLK. Also a
20 ms delay is required after every EEPROM write ac-
cess before a new transaction of any kind is started
(this includes read and write to the register bank).
t
sclkH
t
sclkL
t
sdataS
t
clk2sdata
t
sdataH
t
clk2sdata
Figure 17: 2W-Interface timing diagram