IC-TW2 Datasheet, PDF (15/30 Pages) IC-Haus GmbH – 8-BIT SIN/COS INTERPOLATION IC WITH INTEGRATED EEPROM

iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
INDEX GATING
The iC-TW2 can interface to a wide range of index gat-
ing sources. Most commonly used are the digital hall
sensor and the MR sensor bridge. The digital Hall sen-
sor provides a large swing input signal to the iC-TW2.
Depending on the polarity of the Hall it is either con-
nected to pin NINZ or PINZ. Most Hall sensors use an
open drain stage pulling the output low in the presence
of a magnetic field. The unused terminal PINZ or NINZ
should be biased to an adequate mid voltage level to
guarantee good noise margin. The iC-TW2 provides
a constant 1.21 V at pin VC that can be used for this
purpose (refer to Figure 6).


 
 
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Figure 7: MR sensor index configuration
Index gating should be calibrated at SIN/COS input fre-

quencies below 5 kHz to minimize the effect of latency.
Timings shown in Table 17 are valid for input frequen-
cies below 5 kHz and f_system of 25 MHz. Once the tim-
ings are satisfied according to Table 17, correct opera-
tion is guaranteed up to the maximum input frequency
as specified in Table 22 on page 19.
Figure 6: Digital Hall sensor index configuration
An MR sensor differential bridge can also be used to
gate the index. Typically, the MR sensor provides a
small signal amplitude. In addition, residual side lobes
are present that can trigger double indexing. The iC-
TW2 provides offset control capability to fine tune the
threshold voltage of the index comparator. This greatly
simplifies end product calibration as variation in sen-
sor offset can be compensated for. Figure 8 shows a
correctly set threshold when using an MR gating sen-
sor. The side lobes are below the threshold line and
no parasitic triggering occurs.
Parameter Description
Condition
*
t_setup
Index window setup time no filter
before rising edge of
8 average
Z_W
16 average
t_hold
Index window hold time no filter
after falling edge of Z_W 8 average
16 average
* Filter register FILTER(1:0)
f_system = 25 MHz, all timings scale with f_system
Refer to Table 22 for more information
min
0.4 µs
0.5 µs
0.7 µs
0.4 µs
0.5 µs
0.7 µs
Table 17: Index gating and timing