IC-LNB_13 Datasheet, PDF (22/35 Pages) IC-Haus GmbH – 18-BIT OPTO ENCODER WITH SPI AND SER/PAR INTERFACES

iC-LNB 18-BIT OPTO ENCODER ^preliminary
WITH SPI AND SER/PAR INTERFACES
CS
SCLK
MOSI
MISO
REQ
OP
OP SV 0-7 SV 8-15 ...
8 cycles
Figure 10: SDAD status
Rev A1, Page 22/35
and a DATA byte. The DATA byte is not available in
iC-LNB and is thus not defined.
CS
SCLK
MOSI
MISO
OP
OP STATUS DATA
8 cycles
If only one slave is connected, the relevant SVALID bit
is placed at bit position 7 in the SVALID byte (SV0,
Figure 11).
CS
SCLK
MOSI
MISO
REQ
OP
00000000
OP SV 0 0 0 0 0 0 0 0
8 cycles
SVALID vector
Figure 11: SDAD status (one slave)
REGISTER status/data
The status of the last REGISTER communication or
the last data transmission can be queried using the
REGISTER status/data command. The STATUS byte
contains the information summarized in Table 14.
STATUS
Bit
7
6..4
3
2
1
0
NB
Name
Description of the status
report
ERROR
OPCODE invalid.
Sensor data was invalid
on readout
-
Reserved
DISMISS
Address refused
FAIL
Data request has failed
BUSY
Slave is busy with a
request
VALID
DATA is valid
Display logic: 1 = true, 0 = false
Table 14: SPI status information
All status bits are updated with each register access.
The ERROR bit is the exception to the rule; this bit
signals whether an error occurred during the last com-
munication with the SPI interface or not.
The master transmits the OPCODE REGISTER sta-
tus/data. iC-LNB immediately passes the OPCODE
on to MISO. iC-LNB then transmits the STATUS byte
Figure 12: REGISTER status/data
Read REGISTER (continuous)
The master transmits the OPCODE Read REGISTER
(cont.). Start address ADR, from which point data is to
be read, is transmitted in the 2nd byte. The slave im-
mediately outputs the OPCODE and address and then
transmits DATA1. The internal address counter is in-
cremented after each data package.
If an error occurs during register readout in continu-
ous mode, i.e. the address is invalid, the requested
data was not valid on data byte clocking, etc., the in-
ternal address counter is incremented no further and
the FAIL error bit is set in the status byte (Table 14).
CS
SCLK
MOSI
MISO
OP ADR
OP ADR DATA1 DATA2 ...
8 cycles
Figure 13: Read REGISTER (cont.)
Write to REGISTER (continuous)
The master transmits the OPCODE Write to REGIS-
TER (cont.). Start address ADR, from which point suc-
cessive data DATA1-DATAn is to be written, is transmit-
ted in the 2nd byte. The slave immediately outputs the
OPCODE, address, and data at MISO. The slave incre-
ments its internal address counter after each DATAn
data package.
If an error occurs during a write to register in contin-
uous mode, i.e. the address is invalid, writing of the
last address data has not finished, etc., the internal ad-
dress counter is incremented no further and the FAIL
error bit is set in the status byte (Table 14).