IC-LNB_13 Datasheet, PDF (17/35 Pages) IC-Haus GmbH – 18-BIT OPTO ENCODER WITH SPI AND SER/PAR INTERFACES

iC-LNB 18-BIT OPTO ENCODER ^preliminary
WITH SPI AND SER/PAR INTERFACES
PROGRAMMING iC-LNB
Rev A1, Page 17/35
REGISTER MAP (RAM)
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Signal calibration
0x00
P00
0
0x01
P01
LCMOD
0x02
P02
0x03
P03
0x04
P04
0x05
P05
LED power control
0x06
P06
LCTYP
Output configuration
0x07
P07
NGRAY
DIR
EPG
0x08
P08
INC(2:0)
Test functions
0x09
P09
NENF
TA(1:0)
FlexCount
0x0A
P0A
0x0B
P0B
INVA
INVB
INVZ
0x0C
P0C
0x0D
P0D
0x0E
P0E
RESIPO(1:0)
Z90
0x0F
P0F
0x10
P10
0x11
P11
NOUTLO STOPFLEX
ENIPO
Status (read only)
0x12
0
0
0
0
Bit 3
Bit 2
Bit 1
Bit 0
GS(5:0)
GC(5:0)
OSP(6:0)
OSN(6:0)
OCP(6:0)
OCN(6:0)
LCSET(5:0)
OSZC(1:0)
RNF
GR(1:0)
SRC(2:0)
TMUX(3:0)
HYS(6:0)
TRIABZ
ZPOS(6:0)
ZPOS(13:7)
RESSUB(6:0)
RESSUB(13:7)
SELABS
NENFLEX
ZPOS(17:14)
RESSUB(17:14)
HYS(7)
0
ERRP
ERRS
POSOK
Table 6: Register layout
Address range
The addresses of iC-LNB available through the SPI in-
terface range from addresses 0x00 to 0x12. As only
the lower five bits of the address byte are evaluated,
with addresses that are greater than 0x1F the device
returns to address range 0x00-0x12.
RAM monitoring (parity check)
The configuration registers in the internal RAM are
constantly monitored by a parity check. Bit 7 of each
address is the parity bit (P00-P11) and is supple-
mented to an even number of ones. The unused bits
are also monitored. A parity error (internal ERRP) is
signaled at pin ERR (see the alarm output section).