IC-LNB_13 Datasheet, PDF (15/35 Pages) IC-Haus GmbH – 18-BIT OPTO ENCODER WITH SPI AND SER/PAR INTERFACES

iC-LNB 18-BIT OPTO ENCODER ^preliminary
WITH SPI AND SER/PAR INTERFACES
Rev A1, Page 15/35
OPERATING CONDITIONS: Shift Register
Operating conditions: VDDA = 4 V to 5.5 V, VDD = 3 V to 5.5 V, GNDA = GND, Tj = -40 °C to 125 °C, unless otherwise specified.
Item Symbol Parameter
No.
Conditions
Min.
Unit
Max.
I101 T_CLK
I102 t_lo
Permissible Clock Period
Hold Time Load Signal:
NSL low before NSL edge lo → hi
see Elec. Char. No.: B05
1/fin()
30
ns
I103 tp3
Propagation Delay:
DOUT (idle state) after NSL lo → hi
Elec. Char. No.: B13
I104 tp4
Propagation Delay:
DOUT stable after clock edge CLK
Elec. Char. No.: B14
I105 t_IC
Setup Time:
DIN stable before CLK lo → hi
30
ns
I106 t_CI
Hold Time:
DIN stable after CLK lo → hi
30
ns
I107 t_hi
Preparation Time:
NSL high before request of position
data (CLK hi → lo)
30
ns
NSL
CLK
DOUT
DIN
T_CLK
tp4
t_IC t_CI
Figure 3: Shift register timing
t_lo
t_hi
tp3