IC-MH_17 Datasheet, PDF (20/26 Pages) IC-Haus GmbH – 12-BIT ANGULAR HALL ENCODER

iC-MH
12-BIT ANGULAR HALL ENCODER
Rev C2, Page 20/26
The property of the RS422 driver of the connected line
can be adjusted in the CFGDR register.
CfgDR(1:0)
Addr. 0x07; bit 1:0
00
10 MHz 4 mA (default)
01
10 MHz 60 mA
10
300 kHz 60 mA
11
3 MHz 20 mA
Table 25: Driver property
Signals with the highest frequency can be transmitted
in the setting CFGDR = ’00’. The driver capability is at
least 4 mA, however it is not designed for a 100 Ω line.
This mode is ideal for connection to a digital input on
the same assembly. With the setting CFGDR = ’01’ the
same transmission speed is available and the driver
power is sufficient for the connection of a line over a
short distance. Steep edges on the output enable a
high transmission rate. A lower slew rate is offered by
the setting CFGDR = ’10’, which is excellent for longer
lines in an electromagnetically sensitive environment.
Use of the setting CFGDR = ’11’ is advisable at medium
transmission rates with a limited driver capability.
TRIHL
00
01
10
11
Addr. 0x07; bit 3:2
Push-Pull Output Stage
Lowside Driver
Highside Driver
Tristate
Table 26: Tristate Register
The drivers consist of a push-pull stage in each case
with low-side and high-side drivers which can each be
activated individually. As a result, open-drain outputs
with an external pull-up resistor can also be realized.
BISS INTERFACE
The BiSS interface with BiSS C protocol is a serial
bidirectional interface used to read out the absolute
position and flags and to parameterize the module. All
BiSS communications are CRC secured. For a detailed
description, see separate BiSS C protocol specification
www.biss-interface.com.
MA
SLI
SLO
CDM
Ack Start CDS D11 D10
D0 nE nW CRC5 CRC4
Data Range
CRC0 Stop
Timeout
Figure 23: BiSS Interface Protocol Frame (Single Cycle Data SCD)
The sensor sends a fixed cycle start sequence contain-
ing the acknowledge, start and control bit followed by
the binary 12 bit sensor data. At lower resolution set-
tings the data word contains leading zeros. The low-ac-
tive error bit nE at ’0’ indicates an error which can be
further identified by reading the status register 0x77.
The following bit nW is always at ’1’ state. Following
the 6 CRC bits the data of the next sensors, if available,
are presented. Otherwise the BiSS master stops gen-
erating clock pulse on the MA line an the sensor runs
into a timeout, indicating the end of communication.
Serial Protocol
Content
Cycle Start Sequence
Length of Sensor Data
CRC Polynomial
CRC Transmission
Max. Data Rate
BiSS C
Ack/Start/CDS
12 bit + nERR + nWARN
0x43 = 0b1000011
inverted transmission
10 MHz
Table 27: BiSS C Protocol
ENSSI
0
1
Addr. 0x05; bit 7
BiSS C protocol
SSI protocol
Table 28: Activation of SSI protocol
In the SSI mode the absolute position is output with 13
bits according to the SSI standard. However, in the SSI