IC-MH_17 Datasheet, PDF (18/26 Pages) IC-Haus GmbH – 12-BIT ANGULAR HALL ENCODER

iC-MH
12-BIT ANGULAR HALL ENCODER
Rev C2, Page 18/26
10°
0°
−10°
A
B
Z
0°
1.4°
0°
The rotating direction can easily be changed with the bit
CFGDIR. When the setting is CCW (counter-clockwise,
CFGDIR = ’0’) the resulting angular position values will
increase when rotation of the magnet is performed as
shown in figure 5. To obtain increasing angular position
values in the CW (clockwise) direction, CFGDIR then
has to be set to ’1’.
Figure 18: Quadrature signals for rotating direction
reversal (hysteresis 1.4°)
At the reversal point at +10°, first the corresponding
edge is generated at A. As soon as an angle of 1.4°
has been exceeded in the other direction in accordance
with the hysteresis, the return edge is again generated
at A first. This means that all edges are shifted by the
same value in the rotating direction.
The internal analog sine and cosine signals which are
available in test mode are not affected by the setting of
CFGDIR. They will always appear as shown in figure 5.
CFGSU
0
1
Addr. 0x08; bit 3
ABZ output "111" during startup
AB instantly counting to actual position
Table 21: Configuration of output startup
CFGZPOS(7:0) Addr. 0x07; bit 7:0
0x0
0°
0x1
1,4°
0x2
2,8°
...
360
256
·CFGZPOS
0xff
358,6°
Table 18: Programming AB zero position
The position of the index pulse Z can be set in 1.4°
steps. An 8-bit register is provided for this purpose,
which can shift the Z pulse once over 360°.
CFGMTD2
0
0
1
1
CFGMTD
0
1
0
1
Minimum edge spacing
500 ns
max. 500 kHz at A
125 ns
max. 2 MHz at A
8 µs
max. 31.25 kHz at A
2 µs
max. 125 kHz at A
Table 19: Minimum edge spacing
Depending on the application, a counter cannot bear
generated pulses while the module is being switched
on. When the supply voltage is being connected, the
current position is determined first. During this phase
the quadrature outputs are constantly set to "111" in the
setting CFGSU = ’0’. In the setting CFGSU = ’1’, edges
are generated at the output until the absolute position
is reached. This enables a detection of the absolute
position with the incremental interface.
The converter for the generation of the commutation
signals can be configured for two and four-pole motors.
Three rectangular signals each with a phase shift of
120° are generated. With two-pole commutation, the
sequence repeats once per rotation. With a four-pole
setting, the commutation sequence is generated twice
per rotation.
CFGPOLE
0
1
Addr. 0x8; bit 1
2-pole commutation
4-pole commutation
The CFGMTB register defines the time in which two
consecutive position events can be output. The de-
fault is a maximum output frequency of 500 kHz on A.
This means that at the highest resolution, speeds of
30,000 rpms can still be correctly shown. In the setting
with an edge spacing of 125 ns, the edges can be gen-
erated even at the highest revolution and the maximum
speed. However, the counter connected to the mod-
ule must be able to correctly process all edges in this
case. The settings with 2 µs and 8 µs can be used for
slower counters. It should be noted then, however, that
at higher resolutions the maximum rotation speed is
reduced.
Table 22: Commutation
The zero position of the commutation, i.e. the rising
edge of the track U, can be set as desired over a rota-
tion. Here 192 possible positions are available. Values
above 0xC0 are the mirrored positions from 0x70.
CFGCOM(7:0)
Addr. 0x09; bit 7:0
0x00
0°
0x01
...
0xBF
1,875°
360ř
192
·
CFGCOM
358,125°
CFGDIR
0
1
Addr. 0x08; bit 5
Rotating direction CCW
Rotating direction CW
Table 23: Commutation
Table 20: Rotating direction reversal