HY57V651620B Datasheet, PDF (8/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

HY57V651620B
AC CHARACTERISTICS I
Parameter
Symbol
-55
Min Max
-6
Min M a x
-7
Min Max
-75
Min M a x
-8
Min Max
-10P
Min M a x
-10S
Min Max
-10
Min M a x
Unit
Note
Operation
tR C
55
-
60
-
70
-
65
-
68
-
70
-
70
-
80
-
ns
RAS Cycle Time
Auto Refresh
tR R C
60
-
60
-
702
-
65
-
68
-
70
-
70
-
96
-
ns
RAS toCAS Delay
tR C D
16.5
-
18
-
20
-
20
-
20
-
20
-
20
-
30
-
ns
RAS Active Time
tR A S
38.5 100K 42 100K 42 120K 45 100K 4 8 100K 50 100K 5 0 100K 50 100K ns
RAS Precharge Time
tR P
16.5
-
18
-
20
-
20
-
20
-
20
-
20
-
30
-
ns
RAS toRAS Bank Active Delay
tR R D
11
-
12
-
14
-
15
-
16
-
20
-
20
-
20
-
ns
CAS toCAS Delay
tC C D
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
Write Command to Data-In Delay tW T L
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
- CLK
Data-In to Precharge Command
tD P L
2
-
2
-
1
-
2
-
2
-
1
-
1
-
1
- CLK
Data-In to Active Command
tD A L
5
-
5
-
4
-
5
-
5
-
3
-
3
-
4
- CLK
DQM to Data-Out Hi-Z
tD Q Z
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
- CLK
DQM to Data-In Mask
tD Q M
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
- CLK
MRS to New Command
tM R D
2
-
2
-
1
-
2
-
2
-
2
-
2
-
2
- CLK
C A S Latency = 3 tP R O Z 3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
3
- CLK
Precharge to
Data Output Hi-Z
C A S Latency = 2 tP R O Z 2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
2
- CLK
Power Down Exit Time
tP D E
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
Self Refresh Exit Time
tS R E
1
-
1
-
1
-
1
-
1
-
1
-
1
-
1
- CLK
1
Refresh Time
tR E F
-
64
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
Note :
1. A new command can be given tRRC after self refresh exit
Rev. 1.9/Apr.01
8