HY57V651620B Datasheet, PDF (7/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

HY57V651620B
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter
Symbol
-55
Min Max
-6
Min Max
-7
Min M a x
-75
Min Max
-8
Min Max
-10P
-10S
-10
Min M a x Min M a x Min M a x
Unit
Note
System clock
cycle time
C A S Latency = 3 tCK3
C A S Latency = 2 tCK2
55
6
7
7.5
8
10
10
10
ns
1000
1000
1000
1000
1000
1000
1000
1000
10
10
10
10
10
10
12
12
ns
Clock high pulse width
tCHW
2.75 -
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.75 -
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
3
-
ns
1
Access time from
clock
C A S Latency = 3
C A S Latency = 2
tAC3
tAC2
-
5.4
-
5.4
-
5.4
-
5.4
-
6
-
6
-
6
-
8
ns
2
-
6
-
6
-
6
-
6
-
6
-
6
-
6
-
8
ns
Data-out hold time
tOH
2.5
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
3
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
3
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
3
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
3
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
1
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1.5
-
1
-
1
-
1
-
1
-
1
-
ns
CLK to data output
in high Z-time
C A S Latency = 3
C A S Latency = 2
tOHZ3
tOHZ2
5.4
5.4
2.7
5.4
3
6
3
6
3
6
3
8
ns
5.4
3
6
3
6
3
6
3
6
3
8
ns
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Rev. 1.9/Apr.01
7