HY57V651620B Datasheet, PDF (2/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

PIN CONFIGURATION
PIN DESCRIPTION
VDD 1
DQ0 2
VDDQ 3
DQ1 4
DQ2 5
VSSQ 6
DQ3 7
DQ4 8
VDDQ 9
DQ5 10
DQ6 11
VSSQ 1 2
DQ7 13
VDD 1 4
LDQM 15
/WE 16
/CAS 17
/RAS 18
/CS 19
BA0 20
BA1 21
A10/AP 22
A0 23
A1 24
A2 25
A3 26
VDD 2 7
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
54
V SS
53
DQ15
52
V SSQ
51
DQ14
50
DQ13
49
V DDQ
48
DQ12
47
DQ11
46
V SSQ
45
DQ10
44
DQ9
43
V DDQ
42
DQ8
41
V SS
40
NC
39
UDQM
38
CLK
37
CKE
36
NC
35
A11
34
A9
33
A8
32
A7
31
A6
30
A5
29
A4
28
V SS
HY57V651620B
PIN
CLK
CKE
CS
BA0,BA1
A0 ~ A11
R A S , C A S, W E
LDQM, UDQM
DQ0 ~ DQ15
V DD /V SS
V D D Q /V S S Q
NC
PIN NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during R A S activity
Selects bank to be read/written during C A S activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS and W E define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Power supply for output buffers
No connection
Rev. 1.9/Apr.01
2