HY57V651620B Datasheet, PDF (1/12 Pages) Hynix Semiconductor – 4 Banks x 1M x 16Bit Synchronous DRAM

HY57V651620B
4 Banks x 1M x 16Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
H Y 5 7 V 6 4 1 6 2 0 H G i s o f f e r i n g f u l l y s y n c h r o n o u s o p e r a t i o n r e f e r e n c e d t o a p o s i t i v e e d g e o f t h e c l o c k . A l l i n p u t s a n d o u t p u t s a r e s y nc h r o -
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
P r o g r a m m a b l e o p t i o n s i n c l u d e t h e l e n g t h o f p i p e l i n e ( R e a d l a t e n c y o f 2 o r 3 ) , t h e n u m b e r o f c o n s e c u t i v e r e a d o r w r i t e c y c l e s i n it i a t e d
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
r e a d o r w r i t e c y c l e s i n p r o g r e s s c a n b e t e r m i n a t e d b y a b u r s t t e r m i n a t e c o m m a n d o r c a n b e i n t e r r u p t e d a n d r e p l a c e d b y a n e w b u r st
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
• Single 3.3±0.3V power supply ^Note)
• All device pins are compatible with LVTTL interface
• JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM or LDQM
• Auto refresh and self refresh
• 4096 refresh cycles / 64ms
• Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
• Programmable CAS Latency ; 2, 3 Clocks
• Internal four banks operation
ORDERING INFORMATION
Part No.
HY57V651620BTC-55
HY57V651620BTC-6
HY57V651620BTC-7
HY57V651620BTC-75
HY57V651620BTC-8
HY57V651620BTC-10P
HY57V651620BTC-10S
HY57V651620BTC-10
HY57V651620BLTC-55
HY57V651620BLTC-6
HY57V651620BLTC-7
HY57V651620BLTC-75
HY57V651620BLTC-8
HY57V651620BLTC-10P
HY57V651620BLTC-10S
HY57V651620BLTC-10
Clock Frequency
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
183MHz
166MHz
143MHz
133MHz
125MHz
100MHz
100MHz
100MHz
Power
Organization Interface
Normal
4Banks x 1Mbits
x16
LVTTL
Low power
Package
400mil 54pin TSOP II
Note : VDD(Min) of HY57V651620B(L)TC-55/6/7 is 3.135V
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 1.9/Apr.01