HY5DW113222FMP Datasheet, PDF (6/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

FUNCTIONAL BLOCK DIAGRAM
(4Banks x 2Mbit x 32 I/O) x 2Chips Double Data Rate Synchronous DRAM
HY5DW113222FM(P)
CLK
/CLK
CKE
CS0
/RAS
/CAS
/WE
DM(0~3)
CLK
/CLK
CKE
CS1
/RAS
/CAS
/WE
DM(0~3)
Bank
Control
Write Data Register
32
DS
2-bit Prefetch Unit
64
2Mx32/Bank0
2Mx32/Bank1
64
32
2Mx32/Bank2
2Mx32/Bank3
Mode
Register
Row
Decoder
DQ[0:31]
A0~A11
BA0,BA1
A0~A11
BA0,BA1
Column
Decoder
Column
Address
Counter
Mode Register
CLK, /CLK
CLK_DLL
DS
DLL
Block
Data Strobe
Transmitter
Data Strobe
Receiver
DQS(0~3)
Rev. 0.1 / Oct. 2004
6