HY5DW113222FMP Datasheet, PDF (22/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

HY5DW113222FM(P)
DC CHARACTERISTICS II (TA=0 to 70^oC, Voltage referenced to VSS = 0V)
Parameter
Sym
bol
Test Condition
Speed
Unit Note
2 22 25 28 33 36 4
Operating Current
One bank; Active - Precharge;
tRC=tRC(min); tCK=tCK(min);
IDD0
DQ,DM and DQS inputs changing
twice per clock cycle; address and
690
650
610
570
540
520
500
mA
1
control inputs changing once per
clock cycle
Operating Current
IDD1
Burst length=2, One bank active
tRC ≥ tRC(min), IOL=0mA
730 690 650 610 580 560 540 mA 1
Precharge Standby
Current in Power Down IDD2P CKE ≤ VIL(max), tCK=min
Mode
100 100 100 100 100 100 100 mA
Precharge Standby
CKE ≥ VIH(min), /CS ≥ VIH(min),
Current in Non Power IDD2N tCK = min, Input signals are
Down Mode
changed one time during 2clks
610 580 550 510 480 470 460 mA
Active Standby Cur-
rent in Power Down
Mode
IDD3P CKE ≤ VIL(max), tCK=min
140 140 140 120 100 100 100 mA
Active Standby Cur-
rent in Non Power
Down Mode
CKE ≥ VIH(min), /CS ≥ VIH(min),
IDD3N tCK=min, Input signals are
changed one time during 2clks
680 640 600 560 540 520 500 mA
Burst Mode Operating
Current
IDD4
tCK ≥ tCK(min), IOL=0mA
All banks active
1190 1120 1050 980 870 810 800 mA 1
Auto Refresh Current
IDD5
tRC ≥ tRFC(min),
All banks active
940 920 900 880 770 760 750 mA 1,2
Self Refresh Current IDD6 ^{CKE ≤ 0.2V}
16 16 16 16 16 16 16 mA
Operating Current -
Four Bank Operation
Four bank interleaving with BL=4,
IDD7 Refer to the following page for 1440 1320 1200 1080 970 860 850 mA
detailed test condition
Note :
1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open.
2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.1 / Oct. 2004
22