HY5DW113222FMP Datasheet, PDF (3/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

HY5DW113222FM(P)
DESCRIPTION
Preliminary
The Hynix HY5DW113222FM(P) is a 536,870,912-bit CMOS Double Data Rate(DDR) Synchronous DRAM which consists
of two 256Mbit(x32) - Multi-chip-, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 16Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• The Hynix HY5DW113222FM(P) guarantee until
200MHz speed at DLL_off condition
• 2.5V +/- 5% VDD and 1.8V +/- 5% VDDQ power
supply
• All inputs and outputs are compatible with SSTL_2
interface
• 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
• Fully differential clock inputs (CK, /CK) operation
• The signals of Chip select control the each chip with
CS0 and CS1, individually.
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
ORDERING INFORMATION
• Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
• All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
• Write mask byte controls by DM (DM0 ~ DM3)
• Programmable /CAS Latency 5 / 4 supported
• Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
• Internal 4 bank operations with single pulsed /RAS
• tRAS Lock-Out function supported
• Auto refresh and self refresh supported
• 4096 refresh cycles / 32ms
(Both chips do refresh operation, simultaneously)
• Half strength and Matched Impedance driver option
controlled by EMRS
Part No.
HY5DW113222FM(P)-2
HY5DW113222FM(P)-22
HY5DW113222FM(P)-25
HY5DW113222FM(P)-28
HY5DW113222FM(P)-33
HY5DW113222FM(P)-36
HY5DW113222FM(P)-4
Power
Supply
VDD 2.5V
VDDQ 1.8V
Clock
Frequency
500MHz
450MHz
400MHz
350MHz
300MHz
275MHz
250MHz
Max Data Rate
1000Mbps/pin
900Mbps/pin
800Mbps/pin
700Mbps/pin
600Mbps/pin
550Mbps/pin
500Mbps/pin
interface
SSTL_2
Package
12mmx12mm
144Ball FBGA
Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.
We'll add "P" character after "FM" for lead free product. For example, the part number of 300MHz Lead free
product is HY5DW113222FM(P) - 33.
Rev. 0.1 / Oct. 2004
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