HY5DW113222FMP Datasheet, PDF (13/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

CKE FUNCTION TRUTH TABLE
HY5DW113222FM(P)
Current
State
SELF
REFRESH¹
POWER
DOWN²
ALL BANKS
IDLE⁴
ANY STATE
OTHER
THAN
ABOVE
CKEn-
1
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
CKEn
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
/CS0
/CS1
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
L
H
L
L
L
L
L
X
X
X
X
X
/RAS
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
L
X
H
H
H
L
L
X
X
X
X
X
/CAS
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
L
X
H
H
L
H
L
X
X
X
X
X
/WE
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
H
X
H
L
X
X
L
X
X
X
X
X
/ADD
Action
X
INVALID
X
Exit self refresh, enter idle after tSREX*
X
Exit self refresh, enter idle after tSREX*
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP, continue self refresh
X
INVALID
X
Exit power down, enter idle*
X
Exit power down, enter idle*
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP, continue power down mode
X
See operation command truth table
X
Enter self refresh*
X
Exit power down*
X
Exit power down*
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
ILLEGAL
X
NOP
X
See operation command truth table
X
ILLEGAL⁵
X
INVALID
X
INVALID
Note :
When CKE=L, all DQ and DQS(0~3) must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
6. * Both CSO & CSI should be emabled, simultaneouly.
Rev. 0.1 / Oct. 2004
13