HY5DW113222FMP Datasheet, PDF (26/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

HY5DW113222FM(P)
AC CHARACTERISTICS - I (continue)
Parameter
Symbol
Row Cycle Time
tRC
Auto Refresh Row Cycle Time
tRFC
Row Active Time
tRAS
Row Address to Column Address Delay for Read tRCDRD
Row Address to Column Address Delay for Write tRCDWR
Row Active to Row Active Delay
tRRD
Column Address to Column Address Delay
tCCD
Row Precharge Time
tRP
Write Recovery Time
tWR
Last Data-In to Read Command
tDRL
Auto Precharge Write Recovery + Precharge Time tDAL
System Clock Cycle Time
CL=4
tCK
Clock High Level Width
tCH
Clock Low Level Width
tCL
Data-Out edge to Clock edge Skew
tAC
DQS-Out edge to Clock edge Skew
tDQSCK
DQS-Out edge to Data-Out edge Skew
tDQSQ
Data-Out hold time from DQS
tQH
Clock Half Period
Data Hold Skew Factor
Input Setup Time
Input Hold Time
Write DQS High Level Width
Write DQS Low Level Width
Clock to First Rising edge of DQS-In
Data-In Setup Time to DQS-In (DQ & DM)
Data-In Hold Time to DQS-In (DQ & DM)
tHP
tQHS
tIS
tIH
tDQSH
tDQSL
tDQSS
tDS
tDH
33
Min
Max
15
-
17
-
10
100K
6
-
3
-
3
-
1
-
6
-
3
-
2
-
9
-
3.3
10
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.35
tHPmin
-tQHS
-
tCH/L
min
-
-
0.35
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85
1.15
0.35
-
0.35
-
36
Min
Max
14
-
16
-
9
100K
5
-
2
-
3
-
1
-
5
-
3
-
2
-
8
-
3.6
10
0.45
0.55
0.45
0.55
-0.6
0.6
-0.6
0.6
-
0.4
tHPmin
-tQHS
-
tCH/L
min
-
-
0.4
0.75
-
0.75
-
0.4
0.6
0.4
0.6
0.85
1.15
0.4
-
0.4
-
4
Min
Max
Unit Note
13
-
CK
15
-
CK
8
100K CK
5
-
CK
2
-
CK
3
-
CK
1
-
CK
5
-
CK
3
-
CK
2
-
CK
8
-
CK
4
10
ns
0.45
0.55 CK
0.45
0.55 CK
-0.6
0.6
ns
-0.6
0.6
ns
-
0.4
ns
tHPmin
-tQHS
-
ns 1,6
tCH/L
min
-
ns 1,5
-
0.4
ns 6
0.75
-
ns 2
0.75
-
ns 2
0.4
0.6 CK
0.4
0.6 CK
0.85
1.15 CK
0.4
-
ns 3
0.4
-
ns 3
Rev. 0.1 / Oct. 2004
26