HY5DW113222FMP Datasheet, PDF (24/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

HY5DW113222FM(P)
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter
Symbol
2
Min Max
22
Min Max
25
Min Max
28
Min Max
Unit Note
Row Cycle Time
tRC
23
-
22
-
19
-
17
- CK
Auto Refresh Row Cycle Time
tRFC
25
-
24
-
21
-
19
- CK
Row Active Time
tRAS
15 100K 14 100K 12 100K 11 100K CK
Row Address to Column Address Delay for Read tRCDRD 8
-
7
-
6
-
6
- CK
Row Address to Column Address Delay for Write tRCDWR 5
-
4
-
3
-
3
- CK
Row Active to Row Active Delay
tRRD
5
-
4
-
4
-
4
- CK
Column Address to Column Address Delay
tCCD
1
-
1
-
1
-
1
- CK
Row Precharge Time
tRP
8
-
7
-
6
-
6
- CK
Write Recovery Time
tWR
5
-
4
-
3
-
3
- CK
Last Data-In to Read Command
tDRL
3
-
2
-
2
-
2
- CK
Auto Precharge Write Recovery + Precharge Time tDAL
13
-
11
-
9
-
9
- CK
System Clock Cycle Time
CL=5
tCK
2
10 2.2 10 2.5 10 2.8 10 ns
Clock High Level Width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge Skew
tAC
-0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 ns
DQS-Out edge to Clock edge Skew
tDQSCK -0.6 0.6 -0.6 0.6 -0.6 0.6 -0.6 0.6 ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.35
-
0.35
-
0.35
-
0.35 ns
Data-Out hold time from DQS
tQH
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
tHPmin
-tQHS
-
ns 1,6
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns 1,5
Data Hold Skew Factor
tQHS
-
0.35
-
0.35
-
0.35
-
0.35 ns 6
Input Setup Time
tIS
0.6
- 0.75 -
0.75
- 0.75 -
ns 2
Input Hold Time
tIH
0.6
- 0.75 -
0.75
- 0.75 -
ns 2
Write DQS High Level Width
tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK
Write DQS Low Level Width
tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 CK
Clock to First Rising edge of DQS-In
tDQSS 0.85 1.15 0.85 1.15 0.85 1.15 0.85 1.15 CK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.35 - 0.35 -
0.35
- 0.35 -
ns 3
Data-In Hold Time to DQS-In (DQ & DM)
tDH
0.35
-
0.35 -
0.35
-
0.35
-
ns 3
Rev. 0.1 / Oct. 2004
24