HY5DW113222FMP Datasheet, PDF (12/30 Pages) Hynix Semiconductor – 512M(16Mx32) GDDR SDRAM

OPERATION COMMAND TRUTH TABLE - IV
HY5DW113222FM(P)
Current
State
WRITE
MODE
REGISTER
ACCESSING
/CS0
/CS1
L
L
L
L
L
H
L
L
L
L
L
L
L
L
/RAS
H
L
L
L
L
X
H
H
H
H
L
L
L
L
/CAS
L
H
H
L
L
X
H
H
L
L
H
H
L
L
/WE
L
H
L
H
L
X
H
L
H
L
H
L
H
L
Address
BA, CA, AP
BA, RA
BA, AP
X
OPCODE
X
X
X
BA, CA, AP
BA, CA, AP
BA, RA
BA, AP
X
OPCODE
Command
WRITE/WRITEAP
ACT
PRE/PALL
AREF/SREF
MRS
DSEL
NOP
BST
READ/READAP
WRITE/WRITEAP
ACT
PRE/PALL
AREF/SREF
MRS
Action
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
NOP - Enter IDLE after tMRD
NOP - Enter IDLE after tMRD
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
ILLEGAL¹¹
Note :
1. H - Logic High Level, L - Logic Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
12. Both of CS0 & CS1 should be enabled in pairs.
13. One of CS0 & CS1 should be enabled, individually.
Rev. 0.1 / Oct. 2004
12