HY29LV400 Datasheet, PDF (18/40 Pages) Hynix Semiconductor – 4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory

HY29LV400
and ignores the command for the specified sec-
tors that are protected.
When the system detects that DQ[7] has changed
from the complement to true data (or “0” to “1” for
erase), it should do an additional read cycle to read
valid data from DQ[7:0]. This is because DQ[7]
may change asynchronously with respect to the
other data bits while Output Enable (OE#) is as-
serted low.
Figure 7 illustrates the Data# Polling test algorithm.
DQ[6] - Toggle Bit I
Toggle Bit I on DQ[6] indicates whether an Auto-
matic Program or Erase algorithm is in progress
or complete, or whether the device has entered
the Erase Suspend mode. Toggle Bit I may be read
at any address, and is valid after the rising edge
of the final WE# pulse in the Program or Erase
command sequence, including during the sector
START
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
Test for DQ[7] = 1?
for Erase Operation
YES
NO
NO
DQ[5] = 1?
YES
Read DQ[7:0]
at Valid Address (Note 1)
DQ[7] = Data?
(Note 2)
Test for DQ[7] = 1?
for Erase Operation
YES
NO
PROGRAM/ERASE
EXCEEDED TIME ERROR
PROGRAM/ERASE
COMPLETE
Notes:
1. During programming , the program address. During sector erase , an
address within any non-protected sector specified for erasure. During
chip erase , an address within any non-protected sector.
2. Recheck DQ[7] since it may change asynchronously to DQ[5].
Figure 7. Data# Polling Test Algorithm
18
erase time-out. The system may use either OE#
or CE# to control the read cycles.
Successive read cycles at any address during an
Automatic Program algorithm operation (including
programming while in Erase Suspend mode)
cause DQ[6] to toggle. DQ[6] stops toggling when
the operation is complete. If a program address
falls within a protected sector, DQ[6] toggles for
approximately one µs after the program command
sequence is written, then returns to reading array
data.
While the Automatic Erase algorithm is operating,
successive read cycles at any address cause
DQ[6] to toggle. DQ[6] stops toggling when the
erase operation is complete or when the device is
placed in the Erase Suspend mode. The host may
use DQ[2] to determine which sectors are erasing
or erase-suspended (see below). After an Erase
command sequence is written, if all sectors se-
lected for erasing are protected, DQ[6] toggles for
approximately 100 µs, then returns to reading ar-
ray data. If at least one selected sector is not pro-
tected, the Automatic Erase algorithm erases the
unprotected sectors, and ignores the selected sec-
tors that are protected.
DQ[2] - Toggle Bit II
Toggle Bit II, DQ[2], when used with DQ[6], indi-
cates whether a particular sector is actively eras-
ing or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the
final WE# pulse in the command sequence. The
device toggles DQ[2] with each OE# or CE# read
cycle.
DQ[2] toggles when the host reads at addresses
within sectors that have been specified for era-
sure, but cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ[6],
by comparison, indicates whether the device is ac-
tively erasing or is in Erase Suspend, but cannot
distinguish which sectors are specified for erasure.
Thus, both status bits are required for sector and
mode information.
Figure 8 illustrates the operation of Toggle Bits I
and II.
DQ[5] - Exceeded Timing Limits
DQ[5] is set to a ‘1’ when the program or erase
time has exceeded a specified internal pulse count
Rev. 1.0/Nov. 01