HY29LV400 Datasheet, PDF (13/40 Pages) Hynix Semiconductor – 4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory

HY29LV400
Notes for Table 6:
1. All values are in hexadecimal. DQ[15:8] are don’t care for unlock and command cycles.
2. All bus cycles are write operations unless otherwise noted.
3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[17:11] are don’t care except as follows:
• For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed.
• For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased.
• For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified.
4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-
erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. The fourth bus cycle is a read cycle.
7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode. It must
also be issued to return to read mode if DQ[5] goes High during a program or erase operation. It is not required for normal
read operations.
8. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
n The Reset command may be written between
the cycles in an Electronic ID command se-
quence to abort that command. As described
above, once in the Electronic ID mode, the
Reset command must be written to return to
the array Read mode.
to a “1”. Attempting to do so may halt the opera-
tion and set DQ[5] to “1”, or cause the Data# Poll-
ing algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show
that the data is still “0”.
Figure 4 illustrates the programming procedure.
Program Command
The system programs the device a word or byte
at a time by issuing the appropriate four-cycle pro-
gram command sequence as shown in Table 6.
The sequence begins by writing two unlock cycles,
followed by the program setup command and,
lastly, the program address and data. This ini-
tiates the Automatic Program algorithm which au-
tomatically provides internally generated program
pulses and verifies the programmed cell margin.
The host is not required to provide further con-
trols or timings during this operation. When the
Automatic Program algorithm is complete, the de-
vice returns to the array Read mode (or to the
Erase Suspend mode if the device was in Erase
Suspend when the Program command was is-
sued). Several methods are provided to allow the
host to determine the status of the programming
operation, as described in the Write Operation
Status section.
Commands written to the device during execution
of the Automatic Program algorithm are ignored.
Note that a hardware reset immediately terminates
the programming operation. To ensure data in-
tegrity, the aborted Program command sequence
should be reinitiated once the reset operation is
complete.
Programming is allowed in any sequence. Only
erase operations can convert a stored “0” to a “1”.
Thus, a bit cannot be programmed from a “0” back
Unlock Bypass/Bypass Program/Bypass Reset
Commands
Unlock bypass provides a faster method for the
host system to program the device. As shown in
Table 6, the Unlock Bypass command sequence
consists of two unlock write cycles followed by a
third write cycle containing the Unlock Bypass
command, 0x20. In the Unlock Bypass mode, a
two-cycle Unlock Bypass Program command se-
quence is used instead of the standard four-cycle
Program sequence to invoke a programming op-
eration. The first cycle in this sequence contains
the Unlock Bypass Program command, 0xA0, and
the second cycle specifies the program address
and data, thus eliminating the initial two unlock
cycles required in the standard Program command
sequence Additional data is programmed in the
same manner.
During the Unlock Bypass mode, only the Unlock
Bypass program and Unlock Bypass Reset com-
mands are valid. To exit the Unlock Bypass mode,
the host must issue the two-cycle Unlock Bypass
Reset command sequence shown in Table 6. The
device then returns to the array Read mode.
Chip Erase Command
The Chip Erase command sequence consists of
two unlock cycles, followed by a set-up command,
two additional unlock cycles and then the Chip
Erase command. This sequence invokes the Au-
Rev. 1.0/Nov. 01
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