HY29LV400 Datasheet, PDF (15/40 Pages) Hynix Semiconductor – 4 Mbit (512K x 8/256K x 16) Low Voltage Flash Memory

internally generated erase pulses and verifies cell
erasure within the proper cell margins. The host
system is not required to provide any controls or
timings during these operations.
After the sector erase data cycle (the sixth bus
cycle) of the command sequence is issued, a sec-
tor erase time-out of 50 µs (min), measured from
the rising edge of the final WE# pulse in that bus
cycle, begins. During this time-out window, an ad-
ditional sector erase data cycle, specifying the
sector address of another sector to be erased, may
be written into an internal sector erase buffer. This
buffer may be loaded in any sequence, and the
number of sectors specified may be from one sec-
tor to all sectors. The only restriction is that the
time between these additional data cycles must
be less than 50 µs, otherwise erasure may begin
before the last data cycle is accepted. To ensure
that all data cycles are accepted, it is recom-
mended that host processor interrupts be disabled
during the time that the additional cycles are be-
ing issued and then be re-enabled afterwards.
If all sectors specified for erasing are protected,
the device returns to reading array data after ap-
proximately 100 µs. If at least one specified sec-
tor is not protected, the erase operation erases
HY29LV400
the unprotected sectors, and ignores the command
for the sectors that are protected.
The system can monitor DQ[3] to determine if the
50 µs sector erase time-out has expired, as de-
scribed in the Write Operation Status section. If
the time between additional sector erase data
cycles can be insured to be less than the time-
out, the system need not monitor DQ[3].
Any command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
then rewrite the command sequence, including any
additional sector erase data cycles. Once the sec-
tor erase operation itself has begun, only the Erase
Suspend command is valid. All other commands
are ignored.
As for the Chip Erase command, note that a hard-
ware reset immediately terminates the sector
erase operation. To ensure data integrity, the
aborted Sector Erase command sequence should
be reissued once the reset operation is complete.
When the Automatic Erase algorithm terminates,
the device returns to the array Read mode. Sev-
eral methods are provided to allow the host to de-
termine the status of the erase operation, as de-
scribed in the Write Operation Status section.
START
Write First Five Cycles of
SECTOR ERASE
Command Sequence
Setup First (or Next) Sector
Address for Erase Operation
Check Erase Status
(See Write Operation Status
Section)
DQ[5] Error Exit
Normal Exit
ERASE COMPLETE
GO TO
ERROR RECOVERY
Write Last Cycle (SA/0x30)
of SECTOR ERASE
Command Sequence
Erase An
YES
Additional Sector?
NO
Sector Erase
Time-out (DQ[3])
Expired?
YES
NO
Sectors which require erasure
but which were not specified in
this erase cycle must be erased
later using a new command
sequence
Figure 6. Sector Erase Procedure
Rev. 1.0/Nov. 01
15