H49R50A-1 Datasheet, PDF (30/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

CLR [m].i
Description
Operation
Affected flag(s)
CLR WDT
Description
Operation
Affected flag(s)
CLR WDT1
Description
Operation
Affected flag(s)
CLR WDT2
Description
Operation
Affected flag(s)
CPL [m]
Description
Operation
Affected flag(s)
HT49R50A-1/HT49C50-1/HT49C50L
Clear bit of data memory
The bit i of the specified data memory is cleared to 0.
[m].i ¬ 0
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
Clear Watchdog Timer
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
WDT ¬ 00H
PDF and TO ¬ 0
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
Preclear Watchdog Timer
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
WDT ¬ 00H*
PDF and TO ¬ 0*
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
Preclear Watchdog Timer
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
WDT ¬ 00H*
PDF and TO ¬ 0*
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
Complement data memory
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
[m] ¬ [m]
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
Rev. 2.00
30
November 29, 2005