H49R50A-1 Datasheet, PDF (18/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R50A-1/HT49C50-1/HT49C50L
Bit No.
0~2
3
4
5
6
7
Label
¾
T0E
T0ON
T0S
T0M0
T0M1
Function
Unused bit, read as ²0²
Defines the TMR0 active edge of the timer/event counter:
In Event Counter Mode (T0M1,T0M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T0M1,T0M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable/disable timer counting
(0=disabled; 1=enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0=RTC outputs; 1= system clock or system clock/4)
To define the operating mode (T0M1, T0M0)
01=Event count mode (External clock)
10=Timer mode (Internal clock)
11=Pulse Width measurement mode (External clock)
00=Unused
TMR0C (0EH) Register
Bit No.
0~2
3
4
5
6
7
Label
¾
T1E
T1ON
T1S
T1M0
T1M1
Function
Unused bit, read as ²0²
Defines the TMR1 active edge of the timer/event counter:
In Event Counter Mode (T1M1,T1M0)=(0,1):
1:count on falling edge;
0:count on rising edge
In Pulse Width measurement mode (T1M1,T1M0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
To enable/disable timer counting
(0= disabled; 1= enabled)
2 to 1 multiplexer control inputs to select the timer/event counter clock source
(0= options clock source; 1= system clock/4)
To define the operating mode (T1M1, T1M0)
01= Event count mode (External clock)
10= Timer mode (Internal clock)
11= Pulse Width measurement mode (External clock)
00= Unused
TMR1C (11H) Register
In the event count or timer mode, the timer/event coun-
ter starts counting at the current contents in the
timer/event counter and ends at FFH. Once an overflow
occurs, the counter is reloaded from the timer/event
counter preload register, and generates an interrupt re-
quest flag (T0F;bit 6 of INTC0, T1F;bit 4 of INTC1).
In the pulse width measurement mode with the val-
ues of the T0ON/T1ON and T0E/T1E bits equal to
one, after the TMR0 (TMR1) has received a transient
from low to high (or high to low if the T0E/T1E bit is
²0²), it will start counting until the TMR0 (TMR1) re-
turns to the original level and resets the
T0ON/T1ON. The measured result remains in the
timer/event counter even if the activated transient
occurs again. In other words, only one cycle mea-
surement can be made until the T0ON/T1ON is set. The
cycle measurement will re-function as long as it receives
further transient pulse. In this operation mode, the
timer/event counter begins counting according not to the
logic level but to the transient edges. In the case of coun-
ter overflows, the counter is reloaded from the
timer/event counter preload register and issues an inter-
rupt request, as in the other two modes, i.e., event and
timer modes.
To enable the counting operation, the Timer ON bit
(T0ON: bit 4 of TMR0C; T1ON: bit 4 of TMR1C) should
be set to 1. In the pulse width measurement mode, the
T0ON/T1ON is automatically cleared after the measure-
ment cycle is completed. But in the other two modes, the
T0ON/T1ON can only be reset by instructions. The
Rev. 2.00
18
November 29, 2005