H49R50A-1 Datasheet, PDF (20/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R50A-1/HT49C50-1/HT49C50L
V DD
W eak
P u ll- u p
D a ta b u s
R e a d I/O
PB Input Ports
P B 0~P B 7
rising edge of the instruction ²MOV A, [m]² (m=12H or
14H). For PA, PC output operation, all data are latched
and remain unchanged until the output latch is rewritten.
When the PA and PC structures are open drain NMOS
type, it should be noted that, before reading data from
the pads, a ²1² should be written to the related bits to
disable the NMOS device. That is executing first the in-
struction ²SET [m].i² (i=0~7 for PA) to disable related
NMOS device, and then ²MOV A, [m]² to get stable data.
After chip reset, these input lines remain at the high level
or are left floating (by options). Each bit of these output
latches can be set or cleared by the ²MOV [m], A²
(m=12H or 16H) instruction.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or to the accumulator. When a PA or PC line is
used as an I/O line, the related PA or PC line options
should be configured as NMOS with or without pull-high
resistor. Once a PA or PC line is selected as a CMOS
output, the I/O function cannot be used.
The input state of a PA or PC line is read from the related
PA or PC pad. When the PA or PC is configured as
NMOS with or without pull-high resistor, one should be
careful when applying a read-modify-write instruction to
PA or PC. Since the read-modify-write will read the en-
tire port state (pads state) firstly, execute the specified
instruction and then write the result to the port data reg-
ister. When the read operation is executed, a fault pad
state (caused by the load effect or floating state) may be
read. Errors will then occur.
There are three function pins that share with the PA port:
PA0/BZ, PA1/BZ and PA3/PFD.
The BZ and BZ are buzzer driving output pair and the
PFD is a programmable frequency divider output. If the
user wants to use the BZ/BZ or PFD function, the related
PA port should be set as a CMOS output. The buzzer
output signals are controlled by PA0 and PA1 data regis-
ters and defined in the following table.
PA1 Data
Register
0
1
X
PA0 Data
Register
PA0/PA1 Pad State
0
PA0=BZ, PA1=BZ
0
PA0=BZ, PA1=0
1
PA0=0, PA1=0
Note: ²X² stands for undefined
The PFD output signal function is controlled by the PA3
data register and the timer/event counter state. The
PFD output signal frequency is also dependent on the
timer/event counter overflow period. The definitions of
PFD control signal and PFD output frequency are listed
in the following table.
LCD Display Memory
The devices provides an area of embedded data mem-
ory for LCD display. This area is located from 40H to
60H of the RAM at Bank 1. Bank pointer (BP; located at
04H of the RAM) is the switch between the RAM and the
LCD display memory. When the BP is set as ²1², any
data written into 40H~60H will effect the LCD display.
When the BP is cleared to ²0², any data written into
40H~60H means to access the general purpose data
memory. The LCD display memory can be read and writ-
ten to only by indirect addressing mode using MP1.
When data is written into the display data area, it is auto-
matically read by the LCD driver which then generates
the corresponding LCD driving signals. To turn the dis-
play on or off, a ²1² or a ²0² is written to the correspond-
ing bit of the display memory, respectively. The figure
illustrates the mapping between the display memory
and LCD pattern for the devices.
COM
40H 41H 42H 43H
5 E H 5 F H 6 0 H B it
0
0
1
1
2
2
3
3
SEG M ENT
0
1
2
3
30 31 32
Display Memory
Timer
OFF
OFF
ON
ON
Timer Preload Value
X
X
N
N
Note: ²X² stands for undefined
²U² stands for unknown
PA3 Data Register
0
1
0
1
PA3 Pad State
U
0
PFD
0
PFD Frequency
X
X
f_INT/[2´(256-N)]
X
Rev. 2.00
20
November 29, 2005