H49R50A-1 Datasheet, PDF (10/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R50A-1/HT49C50-1/HT49C50L
Stack Register - STACK
The stack register is a special part of the memory used
to save the contents of the program counter. The stack
is organized into 6 levels and is neither part of the data
nor part of the program, and is neither readable nor
writeable. Its activated level is indexed by a stack
pointer (SP) and is neither readable nor writeable. At a
commencement of a subroutine call or an interrupt ac-
knowledgment, the contents of the program counter is
pushed onto the stack. At the end of the subroutine or in-
terrupt routine, signaled by a return instruction (RET or
RETI), the contents of the program counter is restored
to its previous value from the stack. After chip reset, the
SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag is recorded but the ac-
knowledgment is still inhibited. Once the SP is decre-
mented (by RET or RETI), the interrupt is serviced. This
feature prevents stack overflow, allowing the program-
mer to use the structure easily. Likewise, if the stack is
full, and a ²CALL² is subsequently executed, a stack
overflow occurs and the first entry is lost (only the most
recent six return addresses are stored).
Data Memory - RAM
The data memory (RAM) is designed with 192´8 bits,
and is divided into two functional groups, namely special
function registers and general purpose data memory,
most of which are readable/writeable, although some
are read only.
Of the two types of functional groups, the special func-
tion registers consist of an Indirect addressing register 0
(00H), a Memory pointer register 0 (MP0;01H), an Indi-
rect addressing register 1 (02H), a Memory pointer reg-
ister 1 (MP1;03H), a Bank pointer (BP;04H), an
Accumulator (ACC;05H), a Program counter lower-or-
der byte register (PCL;06H), a Table pointer
(TBLP;07H), a Table higher-order byte register
(TBLH;08H), a Real time clock control register
(RTCC;09H), a Status register (STATUS;0AH), an Inter-
rupt control register 0 (INTC0;0BH), a Timer/Event
Counter 0 (TMR0;0DH), a Timer/Event Counter 0 con-
trol register (TMR0C;0EH), a Timer/Event Counter 1
(TMR1;10H), a Timer/Event Counter 1 control register
(TMR1C;11H), I/O registers (PA;12H, PB;14H,
PC;16H), and Interrupt control register 1 (INTC1;1EH).
On the other hand, the general purpose data memory,
addressed from 60H to FFH, is used for data and control
information under instruction commands.
The areas in the RAM can directly handle arithmetic,
logic, increment, decrement, and rotate operations. Ex-
cept some dedicated bits, each bit in the RAM can be
set and reset by ²SET [m].i² and ²CLR [m].i². They are
also indirectly accessible through the Memory pointer
register 0 (MP0;01H) or the Memory pointer register 1
(MP1;03H).
00H
In d ir e c t A d d r e s s in g R e g is te r 0
01H
M P0
02H
In d ir e c t A d d r e s s in g R e g is te r 1
03H
M P1
04H
BP
05H
ACC
06H
PCL
07H
TB LP
08H
TB LH
09H
R TC C
0A H
STATU S
0B H
IN T C 0
0C H
0D H
TM R 0
0E H
TM R 0C
0FH
10H
TM R 1
11H
TM R 1C
12H
PA
13H
14H
PB
15H
16H
PC
17H
18H
19H
1A H
1B H
1C H
1D H
1E H
IN T C 1
1FH
S p e c ia l P u r p o s e
D a ta M e m o ry
:U nused.
R e a d a s ²0 0 ²
5FH
60H
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
FFH
RAM Mapping
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
eration of [00H] and [02H] accesses the RAM pointed to
by MP0 (01H) and MP1(03H) respectively. Reading lo-
cation 00H or 02H indirectly returns the result 00H.
While, writing it indirectly leads to no operation.
The function of data movement between two indirect ad-
dressing registers is not supported. The memory pointer
registers, MP0 and MP1, are both 8-bit registers used to
access the RAM by combining corresponding indirect
addressing registers. MP0 can only be applied to data
memory, while MP1 can be applied to data memory and
LCD display memory.
Rev. 2.00
10
November 29, 2005