H49R50A-1 Datasheet, PDF (15/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R50A-1/HT49C50-1/HT49C50L
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following.
· The system oscillator turns off but the WDT oscillator
keeps running (if the WDT oscillator or the real time
clock is selected).
· The contents of the on-chip RAM and of the registers
remain unchanged.
· The WDT is cleared and start recounting (if the WDT
clock source is from the WDT oscillator or the real time
clock oscillator).
· All I/O ports maintain their original status.
· The PDF flag is set but the TO flag is cleared.
· LCD driver is still running (if the WDT OSC or RTC
OSC is selected).
The system quits the HALT mode by an external reset, an
interrupt, an external falling edge signal on port A, or a
WDT overflow. An external reset causes device initializa-
tion, and the WDT overflow performs a ²warm reset². Af-
ter examining the TO and PDF flags, the reason for chip
reset can be determined. The PDF flag is cleared by sys-
tem power-up or by executing the ²CLR WDT² instruc-
tion, and is set by executing the ²HALT² instruction. On
the other hand, the TO flag is set if WDT time-out occurs,
and causes a wake-up that only resets the program
counter and SP, and leaves the others at their original
state.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by option. Awakening from an I/O port stimulus,
the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
quences may occur. If the related interrupt is disabled or
the interrupt is enabled but the stack is full, the program
resumes execution at the next instruction. But if the in-
terrupt is enabled, and the stack is not full, the regular in-
terrupt response takes place.
When an interrupt request flag is set before entering the
²HALT² status, the system cannot be awaken using that
interrupt.
If wake-up events occur, it takes 1024 t_SYS (system
clock period) to resume normal operation. In other
words, a dummy period is inserted after the wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution is delayed by
more than one cycle. However, if the Wake-up results in
the next instruction execution, the execution will be per-
formed immediately after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
There are three ways in which reset may occur.
· RES is reset during normal operation
· RES is reset during HALT
· WDT time-out is reset during normal operation
The WDT time-out during HALT differs from other chip
reset conditions, for it can perform a ²warm reset² that
resets only the program counter and SP and leaves the
other circuits at their original state. Some registers re-
main unaffected during any other reset conditions. Most
registers are reset to the ²initial condition² once the re-
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
Note:
²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
avoid noise interference.
TO PDF
RESET Conditions
0 0 RES reset during power-up
u u RES reset during normal operation
0 1 RES Wake-up HALT
1 u WDT time-out during normal operation
1 1 WDT Wake-up HALT
Note: ²u² means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the sys-
tem awakes from the HALT state. Awaking from the
HALT state, the SST delay is added.
An extra SST delay is added during the power-up period
and any wakeup from the HALT may enable only the
SST delay.
The functional unit chip reset status is shown below.
Program Counter 000H
Interrupt
Disabled
Prescaler, Divider Cleared
WDT, RTC,
Time base
Cleared. After master reset,
WDT starts counting
Timer/Event Counter Off
Input/output ports Input mode
Stack Pointer
Points to the top of the stack
Rev. 2.00
15
November 29, 2005