H49R50A-1 Datasheet, PDF (19/45 Pages) Holtek Semiconductor Inc – LCD Type 8-Bit MCU

HT49R50A-1/HT49C50-1/HT49C50L
overflow of the Timer/Event Counter 0/1 is one of the
wake-up sources and can also be applied to a PFD (Pro-
grammable Frequency Divider) output at PA3 by option.
Only one PFD (PFD0 or PFD1) can be applied to PA3 by
options. If PA3 is set as PFD output, there are two types of
selections; One is PFD0 as the PFD output, the other is
PFD1 as the PFD output. PFD0, PFD1 are the timer over-
flow signals of the Timer/Event Counter 0, Timer/Event
Counter 1 respectively. No matter what the operation
mode is, writing a 0 to ET0I or ET1I disables the related in-
terrupt service. When the PFD function is selected, exe-
cuting ²CLR [PA].3² instruction to enable PFD output and
executing ²SET [PA].3² instruction to disable PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is turn on, data written to the
timer/event counter is kept only in the timer/event coun-
ter preload register. The timer/event counter still contin-
ues its operation until an overflow occurs.
When the timer/event counter (reading TMR0/TMR1) is
read, the clock is blocked to avoid errors. As this may re-
sults in a counting error, blocking of the clock should be
taken into account by the programmer.
It is strongly recommended to load a desired value into
the TMR0/TMR1 register first, then turn on the related
timer/event counter for proper operation. Because the
initial value of TMR0/TMR1 is unknown.
Due to the timer/event scheme, the programmer should
pay special attention on the instruction to enable then
disable the timer for the first time, whenever there is a
need to use the timer/event function, to avoid
unpredicatable result. After this procedure, the
timer/event function can be operated normally. The ex-
ample given below, using two 8-bit width Timer¢s (timer
0 ;timer 1) cascade into 16-bit width.
D a ta b u s
W r ite
C h ip R e s e t
D
Q
CK Q
S
START:
mov a, 09h ; Set ET0I & EMI bits to
mov intc0, a ; enable timer 0 and
; global interrupt
mov a, 01h ; Set ET1I bit to enable
mov intc1, a ; timer 1 interrupt
mov a, 80h ; Set operating mode as
mov tmr1c, a ; timer mode and select mask
; option clock source
mov a, 0a0h ; Set operating mode as timer
mov tmr0c, a ; mode and select system
; clock/4
set tmr1c.4 ; Enable then disable timer 1
clr tmr1c.4 ; for the first time
mov a, 00h
mov tmr0, a
mov a, 00h
mov tmr1, a
; Load a desired value into
; the TMR0/TMR1 register
;
;
set tmr0c.4 ; Normal operating
set tmr1c.4 ;
END
Input/Output Ports
There are a 12-bit bidirectional input/output port, an 8-bit
input port in the devices, labeled PA, PB and PC which
are mapped to [12H], [14H] and [16H] of the RAM, re-
spectively. PA0~PA3 can be configured as CMOS (out-
put) or NMOS (input/output) with or without pull-high
resistor by option. PA4~PA7 are always pull-high and
NMOS (input/output). If you choose NMOS (input), each
bit on the port (PA0~PA7) can be configured as a
wake-up input. PB can only be used for input operation.
The contents of PC4~PC7 are unknown. PC can be con-
figured as CMOS output or NMOS input/output with or
without pull-high resistor by option. All the port for the in-
put operation (PA, PB and PC), these ports are
non-latched, that is, the inputs should be ready at the T2
V DD
V DD
W eak
P u ll- u p
O p tio n
(P A 0 ~
P A 3,P C )
O p tio n
(P A 0 ~ P A 3 , P C )
P A 0~P A 7
P C 0~P C 3
R e a d I/O
S y s te m W a k e - u p ( P A o n ly )
O p tio n
PA, PC Input/Output Ports
Rev. 2.00
19
November 29, 2005