HD404449 Datasheet, PDF (94/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
000. Therefore, if a write is performed during data transfer, the serial 2 interrupt request flag (IFS2: $023,
bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the SM2A
read instruction must be executed at least two cycles after that.
Serial mode register 2A (SM2A: $01B)
Bit
Initial value
Read/Write
Bit name
3
0
W
SM2A3
2
0
W
SM2A2
1
0
W
SM2A1
0
0
W
SM2A0
SM2A3
0
1
R5₁/SCK₂
mode selection
R5₁
SCK₂
SM2A2
0
1
SM2A1 SM2A0
0
0
1
1
0
1
0
0
1
1
0
1
SCK₂
Output
Output
Input
Prescaler
Clock source division ratio
Prescaler
Refer to
table 29
System clock —
External clock —
Figure 77 Serial Mode Register 2A (SM2A)
Serial Mode Register 2B (SM2B: $01C): This register has the following functions (figure 78).
• Serial interface 2 prescaler division ratio selection
• Serial interface 2 output level control in idle states
• R5₃/SO₂ pin PMOS control
Serial mode register 2B (SM2B: $01C) is a 3-bit write-only register. It cannot be written during serial
interface 2 data transfer. Bit 0 (SM2B0) and bit 2 (SM2B2) is reset to $0 by MCU reset.
By setting bit 0 (SM2B0) of this register, the serial interface 2 prescaler division ratio of serial interface 2 is
selected. By resetting bit 1 (SM2B1), the output level of the SO₂ pin is controlled in idle states of serial
interface 2. The output level changes at the same time that SM2B1 is written to.
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