HD404449 Datasheet, PDF (83/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 67.
 STS wait state (serial interface 2 is in SM2A read wait state)
 Transmit clock wait state
 Transfer state
 Continuous clock output state (only in internal clock mode)
The operation state of serial interface 2 is the same as serial interface 1 except that the STS instruction of
serial interface 1 changes to SM2A read. The following shows the operation state of serial interface 1.
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 67). In STS
wait state, serial interface 1 is initialized and the transmit clock is ignored. If the STS instruction is then
executed (01, 11), serial interface 1 enters transmit clock wait state.
External clock mode
STS wait state
(Octal counter = 000,
transmit clock disabled)
00 MCU reset
SM1A write 04
01 STS instruction
06 SM1A write (IFS ^← 1)
Transmit clock wait state
(Octal counter = 000)
02 Transmit clock
03
8 transmit clocks
05
STS instruction (IFS ^← 1)
Transfer state
(Octal counter = 000)
Internal clock mode
SM1A write
18
STS wait state
(Octal counter = 000,
transmit clock disabled)
10 MCU reset
Continuous clock output state
(PMRA 0, 1 = 00)
SM1A write 14
11 STS instruction
Transmit clock 17
Transmit clock wait state
(Octal counter = 000)
12 Transmit clock
15
STS instruction (IFS ← 1)
13 8 transmit clocks
16 SM1A write (IFS ←1)
Transfer state
(Octal counter = 000)
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 67 Serial Interface State Transitions
• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the
falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12)
increments the octal counter, shifts serial data register 1 (SR1L: $006, SR1U: $007), and enters the
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