HD404449 Datasheet, PDF (87/123 Pages) Hitachi Semiconductor – HD404449 SERIES

Transfer completion
(IFS1 ← 1)
Interrupts inhibited
IFS1 ^← 0
SM1A write
Yes
IFS1 = 1
No
Normal
termination
HD404449 Series
Transmit clock
error processing
Transmit clock error detection flowchart
State
Transmit clock
wait state
Transfer state
Transmit clock wait state
Transfer state
SCK ₁ pin
(input)
SM1A
write
IFS1
Noise
1
2
3
4
5
6
7
8
Transfer state has been
entered by the transmit clock
error. When SM1A is written,
IFS1 is set.
Flag set because octal
counter reaches 000.
Flag reset at
transfer completion.
Transmit clock error detection procedures
Figure 69 Transmit Clock Error Detection
87