HD404449 Datasheet, PDF (25/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 12.
Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC
0
1
Interrupt Request
Enabled
Disabled (Masked)
Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling edge of signals input to EVND when the input capture function is used, as listed in table
13.
Table 13 Timer D Interrupt Request Flag (IFTD: $003, Bit 0)
IFTD
0
1
Interrupt Request
No
Yes
Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 14.
Table 14 Timer D Interrupt Mask (IMTD: $003, Bit 1)
IMTD
0
1
Interrupt Request
Enabled
Disabled (Masked)
Serial Interrupt Request Flags (IFS1: $003, Bit 2; IFS2: $023, Bit 2) Set when data transfer is
completed or when data transfer is suspended, as listed in table 15.
Table 15 Serial Interrupt Request Flag (IFS1: $003, Bit 2; IFS2: $023, Bit 2)
IFS1, IFS2
0
1
Interrupt Request
No
Yes
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