HD404449 Datasheet, PDF (74/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:
$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing
0.
By selecting the input capture operation, pin R3₂/TOD is set to R3₂ and timer D is reset to $00.
Registers for Timer D Operation: By using the following registers, timer D operation modes are selected
and the timer D count is read and written.
 Timer mode register D1 (TMD1: $010)
 Timer mode register D2 (TMD2: $015)
 Timer write register D (TWDL: $011, TWDU: $012)
 Timer read register D (TRDL: $011, TRDU: $012)
 Port mode register C (PMRC: $025)
 Detection edge select register 2 (ESR2: $027)
• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-
running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 59.
It is reset to $0 by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output
mode and input capture operation as shown in figure 60. It is reset to $0 by MCU reset.
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