HD404449 Datasheet, PDF (81/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
1 is initialized by writing data to serial mode register 1A, and serial interface 2 is initialized by writing data
to serial mode register 2A. Refer to the following section Registers for Serial Interface for details.
Pin Setting: The R4₁/SCK₁ pin is controlled by writing data to serial mode register 1A (SM1A: $005).
The R5₁/SCK₂ pin is controlled by writing data to serial mode register 2A (SM2A: $01B). Pins R4₂/SI₁,
R4₃/SO₁, R5₂/SI₂, and R5₃/SO₂ are controlled by writing data to port mode register A (PMRA: $004). Refer
to the following section Registers for Serial Interface for details.
Transmit Clock Source Setting: The transmit clock source of serial interface 1 is set by writing data to
serial mode register 1A (SM1A: $005) and serial mode register 1B (SM1B: $028). The transmit clock
source of serial interface 2 is set by writing data to serial mode register 2A (SM2A: $01B) and serial mode
register 2B (SM2B: $01C). Refer to the following section Registers for Serial Interface for details.
Data Setting: Transmit data of serial interface 1 is set by writing data to serial data register 1 (SR1L:
$006, SR1U: $007). Transmit data of serial interface 2 is set by writing data to serial data register 2
(SR2L: $01D, SR2U: $01E). Receive data of serial interface 1 is obtained by reading the contents of serial
data register 1. Receive data of serial interface 2 is obtained by reading the contents of serial data register
2. The serial data is shifted by each serial interface transmit clock and is input from or output to an external
system.
The output level of the SO₁ and SO₂ pins is invalid until the first data of each serial interface is output after
MCU reset, or until the output level control in idle states is performed.
Transfer Control: Serial interface 1 is activated by the STS instruction. Serial interface 2 is activated by
a dummy read of serial mode register 2A (SM2A: $01B), which will be referred to as SM2A read. The
octal counter is reset to 000 by the STS instruction (serial interface 2 is SM2A read), and it increments at
the rising edge of the transmit clock for each serial interface. When the eighth transmit clock signal is
input or when serial transmission/reception is discontinued, the octal counter is reset to 000, the serial 1
interrupt request flag (IFS1: $003, bit 2) for serial interface 1 and serial 2 interrupt request flag (IFS2:
$023, bit 2) for serial interface 2 are set, and the transfer stops.
When the prescaler output is selected as the transmit clock of serial interface 1, the transmit clock
frequency is selected as 4t_cyc to 8192t_cyc by setting bits 0 to 2 (SM1A0–SM1A2) of serial mode register 1A
(SM1A: $005) and bit 0 (SM1B0) of serial mode register 1B (SM1B: $028) as listed in table 29. When the
prescaler output is selected as the transmit clock of serial interface 2, the transmit clock frequency is
selected as 4t_cyc to 8192t_cyc by setting bits 0 to 2 (SM2A0– SM2A2) of serial mode register 2A (SM2A:
$01B) and bit 0 (SM2B0) of serial mode register 2B (SM2B: $01C).
Note: To start serial interface 2, simply read serial mode register 2A by using the instruction that
compares serial mode register 2A (SM2A: $01B) with the accumulator.
Serial mode register 2A (SM2A: $01B) is a read-only register, so $0 can be read.
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