HD404449 Datasheet, PDF (20/123 Pages) Hitachi Semiconductor – HD404449 SERIES

HD404449 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
Interrupt
Control Bit INT₀
IE
1
INT₁
1
Timer A
1
Timer B or Timer C or Timer D or Serial 1 or
INT₂
INT₃
A/D
Serial 2
1
1
1
1
IF0 ^. IM0
1
0
0
0
0
0
0
IF1 ^. IM1
*
1
0
0
0
0
0
IFTA ^. IMTA *
*
1
0
0
0
0
IFTB ^. IMTB *
*
*
1
0
0
0
+ IF2 ^. IM2
IFTC ^. IMTC *
*
*
*
1
0
0
+ IF3 ^. IM3
IFTD ^. IMTD *
*
*
*
*
1
0
+ IFAD ^. IMAD
IFS1 ^. IMS1 *
*
*
*
*
*
1
+ IFS2 ^. IMS2
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
1
2
3
4
5
6
Instruction
execution*
Interrupt
acceptance
Stacking
IE reset
Vector address
generation
Execution of JMPL
instruction at vector address
Note: *The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 10 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
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