GS81314LQ19 Datasheet, PDF (9/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
Configuration Registers
These devices utilize a set of registers for device configuration. The configuration registers are written via Register Write Mode,
which is initiated by asserting MRW High and R Low. When Register Write Mode is utilized, up to sixteen distinct 6-bit registers
can be programmed using SDR timing on the SA[10:1] address input pins. The D data input pins are not used.
Note: Register Write Mode only provides the ability to write the configuration registers. The ability to read the configuration regis-
ters is provided via a private JTAG instruction and register. Please contact GSI for more information.
Register Write Mode can be utilized in two ways:
1. Asynchronous Method: MRW is driven asynchronously, such that is does not meet setup and hold time specs to CK.
2. Synchronous Method: MRW is driven synchronously, such that is meets setup and hold time specs to CK.
Regardless how Register Write Mode is utilized, at least 16 NOPs must be initiated before beginning a Register Write sequence, to
ensure any previous Read and Write operations are completed before the sequence begins. And, at least 16 NOPs must be initiated
after completing a Register Write sequence and before initiating Read and Write operations, and before utilizing Loopback Mode,
to allow sufficient time for the newly programmed register settings to take effect.
Register Write Mode Utilization - Asynchronous Method
Register Write Mode can be utilized asynchronously up to the full operating speed of the device. When Register Write Mode is uti-
lized asynchronously, there are two cases to consider:
1. Pre Input Training: SA[10:1], R, W are driven such that they do not meet setup and hold time specs to CK.
2. Post Input Training: SA[10:1], R, W are driven such that they meet setup and hold time specs to CK.
Each case is examined separately below.
Pre Input Training Requirements
In this case, MRW, R, W, and SA[10:1] are all driven asynchronously. When Register Write Mode is utilized in this manner, only
one register can be programmed during any particular instance that MRW is asserted High.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write sequence.
• MRW High must meet minimum pulse width requirements (tMRWPW).
• R Low and SA[10:1] Valid must meet minimum setup time requirements (tMRWS) to MRW High.
• R Low and SA[10:1] Valid must meet minimum hold time requirements (tMRWH) from MRW Low.
• W High must also meet minimum setup time requirements (tMRWS) to MRW High, if inadvertent memory writes are to be pre-
vented during the Register Write process. Otherwise, W state is “don’t care”.
• W High must also meet minimum hold time requirements (tMRWH) from MRW Low, if inadvertent memory writes are to be
prevented during the Register Write process. Otherwise, W state is “don’t care”.
Note: tMRWPW = tMRWS = tMRWH = 4 cycles (minimum).
Note: Inadvertent memory reads will occur while MRW and R are Low during the Register Write process. The memory reads are
harmless, and can be ignored.
Rev: 1.02 3/2016
9/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology