GS81314LQ19 Datasheet, PDF (11/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
Register Write Mode Utilization - Synchronous Method
Register Write Mode can also be utilized synchronously up to the full operating speed of the device. However, MRW cannot be
trained using Loopback Mode, so the ability to use it synchronously may be limited to slower operating frequencies where the lack
of training capability is less problematic for the user.
In this case, MRW, R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and hold time specs to CK). When
Register Write Mode is utilized in this manner, multiple registers can be programmed in successive cycles. The timing diagrams
below arbitrarily show four registers programmed in successive cycles, but in practice it can be any number greater than or equal to
one.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write(s).
• MRW must be driven High (synchronously), R must be driven Low (synchronously), and SA[10:1] must be driven Valid (syn-
chronously) for each Register Write.
• W state is a “don’t care” (synchronously) for each Register Write.
Synchronous Register Write Timing Diagram
Read / Write
16 NOPs
Register Write Mode
16 NOPs
Read / Write
CK
t_IVKH t_KHIX
SA[10:1] V
Reg #a Reg #b Reg #c Reg #d
V
V
WV
X
X
X
X
V
V
RV
t_RVKH t_KHRX
V
V
MRW
Rev: 1.02 3/2016
11/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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