GS81314LQ19 Datasheet, PDF (10/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
Post Input Training Requirements
In this case, MRW is driven asynchronously, whereas R, W, and SA[10:1] are all driven synchronously (i.e. they all meet setup and
hold time specs to CK). When Register Write Mode is utilized in this manner, multiple registers can be programmed during any
particular instance that MRW is asserted High. The timing diagrams below arbitrarily show four registers programmed while MRW
is asserted High, but in practice it can be any number greater than or equal to one.
The requirements for this usage case are as follows:
• At least 16 NOPs must be initiated before and after the Register Write(s).
• MRW High must meet minimum setup time requirements (tMRWS) to the CK that generates the first Register Write.
• MRW High must meet minimum hold time requirements (tMRWH) from the CK that generates the first NOP after the last Reg-
ister Write.
• R must be driven Low (synchronously) and SA[10:1] must be driven Valid (synchronously) for each Register Write.
• W state is a “don’t care” (synchronously) for each Register Write.
Note: tMRWS = tMRWH = 4 cycles (minimum).
Asynchronous Register Write Timing Diagram - Pre Input Training
16 NOPs
Register Write Mode
16 NOPs
CK
t_MRWS
t_MRWPW
t_MRWH
SA[10:1]
Register #n
W
Must be “high” to prevent memory write; “don’t care” otherwise
R
MRW
Asynchronous Register Write Timing Diagram - Post Input Training
Read / Write
16 NOPs
Register Write Mode
16 NOPs
CK
t_IVKH t_KHIX
Read / Write
SA[10:1] V
Reg #a Reg #b Reg #c Reg #d
V
V
WV
X
X
X
X
V
V
RV
t_MRWS
t_MRWH
V
V
MRW
Rev: 1.02 3/2016
10/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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