GS81314LQ19 Datasheet, PDF (4/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
Pin Description
Symbol
Description
SA[21:0]
D[35:0]
Q[35:0]
QVLD[1:0]
CK, CK
KD[1:0],
KD[1:0]
CQ[1:0],
CQ[1:0]
R
W
MRW
PLL
RST
ZQ
ZT
RCS
Address — Read address is registered on CK and write address is registered on CK.
Write Data — Registered on KD and KD during Write operations.
D[17:0] - x18 and x36.
D[35:18] - x36 only.
Read Data — Aligned with CQ and CQ during Read operations.
Q[17:0] - x18 and x36.
Q[35:18] - x36 only.
Read Data Valid — Driven high one half cycle before valid read data.
Primary Input Clocks — Dual single-ended. Used for latching address and control inputs, for internal timing
control, and for output timing control.
Write Data Input Clocks — Dual single-ended. Used for latching write data inputs.
KD0, KD0: latch D[17:0] in x36, and D[8:0] in x18.
KD1, KD1: latch D[35:18] in x36, and D[17:9] in x18.
Read Data Output Clocks — Free-running output (echo) clocks, tightly aligned with read data outputs.
Facilitate source-synchronous operation.
CQ0, CQ0: align with Q[17:0] in x36, and Q[8:0] in x18.
CQ1, CQ1: align with Q[35:18] in x36, and Q[17:9] in x18.
Read Enable — Registered on CK. See the Clock Truth Table for functionality.
Write Enable — Registered on CK. See the Clock Truth Table for functionality.
Mode Register Write — Registered onCK. Can be used synchronously or asynchronously to enable Reg-
ister Write Mode. See the State and Clock Truth Tables for functionality.
PLL Enable — Weakly pulled High internally.
PLL = 0: disables internal PLL.
PLL = 1: enables internal PLL.
Reset — Holds the device inactive and resets the device to its initial power-on state when asserted High.
Weakly pulled Low internally.
Driver Impedance Control Resistor Input — Must be connected to V_SS through an external resistor RQ to
program driver impedance.
ODT Impedance Control Resistor Input — Must be connected to V_SS through an external resistor RT to
program ODT impedance.
Current Source Resistor Input — Must be connected to V_SS through an external 2K resistor to provide
an accurate current source for the PLL.
Type
Input
Input
Output
Output
Input
Input
Output
Input
Input
Input
Input
Input
Input
Input
Input
Rev: 1.02 3/2016
4/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology