GS81314LQ19 Datasheet, PDF (20/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
State Truth Table
RST MRW LBKE R W SA D
1
X
X
X
X
X
X
0
1
X
0
X
V
X
0
0
1
X
X
X
X
0
1
X
1
See Clock Truth Table
0
0
0
X
Note: 1 = High; 0 = Low; V = Valid; X = don’t care.
SRAM State
Reset
Register Write Mode
Loopback Mode
Memory Mode
(Read, Write, NOP)
Q
NOP State
Undefined
Loopback
See Clock Truth
Table
Clock Truth Table
SA
MRW R
W
Current Operation
D
Q
CK
CK
CK
CK
CK
KD
KD
CQ
CQ
(t_n)
(t_n+½)
(t_n)
(t_n)
(t_n)
(t_n)
(t_n)
(t_n+½)
(t_n+5)
(t_n+5½)
X
X
0
1
1
NOP
X
X
0
X
V
0
1
0
Write Only
D1
D2
0
V
X
0
0
1
Read Only
X
X
Q1
Q2
V
V
0
0
0
Read + Write
D1
D2
Q1
Q2
V
V
1
0
X
Register Write
X
X
Undefined
V
V
1
1
X
NOP
X
X
0
Notes:
1. 1 = High; 0 = Low; V = Valid; X = don’t care.
2. D1 and D2 indicate the first and second pieces of write data transferred during Write operations.
3. Q1 and Q2 indicate the first and second pieces of read data transferred during Read operations.
4. Q pins are driven Low for one cycle in response to NOP and Write Only commands, 5 cycles after the command is sampled.
Rev: 1.02 3/2016
20/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology