GS81314LQ19 Datasheet, PDF (8/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
PLL Operation
A PLL is implemented in these devices to control all output timing. It uses the CK input clock as a source, and is enabled when all
of the following conditions are met:
1. RST is de-asserted Low, and
2. Either the PLL Enable pin (PLL) or the PLL Enable register bit (PLE) is asserted High, and
3. CK cycle time  t_KHKH (max), as specified in the AC Timing Specifications section.
Once enabled, the PLL requires 64K stable clock cycles in order to lock/synchronize properly.
When the PLL is enabled, it aligns output clocks and read data to input clocks (with some fixed delay), and it generates all
mid-cycle output timing. See the Output Timing section for more information.
The PLL can tolerate changes in input clock frequency due to clock jitter (i.e. such jitter will not cause the PLL to lose lock/
synchronization), provided the cycle-to-cycle jitter does not exceed 200ps (see “t_KJITcc” in the AC Timing Specifications section
for more information). However, the PLL must be resynchronized (i.e. disabled and then re-enabled) whenever the nominal input
clock frequency is changed.
The PLL is disabled when any of the following conditions are met:
1. RST is asserted High, or
2. Both the PLL Enable pin (PLL) and the PLL Enable register bit (PLE) are deasserted Low, or
3. CK is stopped for at least 30ns, or CK cycle time  30ns.
On-Chip Error Correction
These devices implement a single-error correct, single-error detect (SEC-SED) ECC algorithm (specifically, a Hamming Code) on
each 18-bit data word transmitted in DDR fashion on each 9-bit data bus (i.e., transmitted on D/Q[8:0], D/Q[17:9], D/Q[26:18],
and D/Q[35:27]). To accomplish this, 5 ECC parity bits (invisible to the user) are utilized per every 18 data bits (visible to the
user). As such, these devices actually comprise 184Mb of memory, of which 144Mb are visible to the user.
The ECC algorithm cannot detect multi-bit errors. However, these devices are architected in such a way that a single SER event
very rarely causes a multi-bit error across any given “transmitted data unit”, where a “transmitted data unit” represents the data
transmitted as the result of a single read or write operation to a particular address. The extreme rarity of multi-bit errors results in
the SER mentioned previously (i.e., <0.002 FITs/Mb, measured at sea level).
Not only does the on-chip ECC significantly improve SER performance, but it can also free up the entire memory array for data
storage. Very often SRAM applications allocate 1/9th of the memory array (i.e., one “error bit” per eight “data bits”, in any 9-bit
“data byte”) for error detection (either simple parity error detection, or system-level ECC error detection and correction).
Depending on the application, such error-bit allocation may be unnecessary in these devices, in which case the entire memory array
can be utilized for data storage, effectively providing 12.5% greater storage capacity compared to SRAMs of the same density not
equipped with on-chip ECC.
Rev: 1.02 3/2016
8/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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