GS81314LQ19 Datasheet, PDF (12/39 Pages) GSI Technology – 144Mb SigmaQuad-IVe™ Burst of 2 Single-Bank ECCRAM™

GS81314LQ19/37GK-933/800
Register Description
As described previously, Register Write Mode provides the ability to program up to sixteen distinct 6-bit configuration registers us-
ing SDR timing on the SA[10:1] address input pins. Specifically, SA[4:1] are used to select one of the sixteen distinct registers, and
SA[10:5] are used to program the six data bits of the selected register.
The registers are defined as follows:
Address
Pin
Bit Usage
Active
Active
Active
Active
Active
Unused
Active
SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1
8G 6G 8J 6J 8M 6M 8P 6P 8T 6T
Register Data Bits
Register Select Bits
DZT[1:0]
RLM
RSVD[2:0]
PLE
LBK[1:0]
LBKE
KDZT[1:0]
CKZT[1:0]
CZT[1:0]
AZT[1:0]
Reserved for GSI Internal Use Only
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
All Others except “111X”
1
1
1
X
Reg #
0
1
2
3
4
5 ~ 13
14 ~ 15
Notes:
1. Unused/unlabeled register bits should be written to “0”.
2. The RSVD[2:0] bits in Register #1 should be written to “100”.
3. Registers #14 and #15 are reserved for GSI internal use only. Users should not access these registers.
Register Bit Definitions
Read Latency Select
RLM
0
Read Latency = 5 cycles
1
reserved
1
POR/RST Default
PLL Enable
PLE
0
Disable PLL, if PLL pin = 0
1
Enable PLL
0
POR/RST Default
Note: The power-on / reset default value of the RLM register bit is “1”. Consequently, Register Write Mode must be used to set the
RLM bit to “0”, to program RL=5 in these devices, prior to issuing Read operations.
Rev: 1.02 3/2016
12/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology