GS4576C36GL-25I Datasheet, PDF (55/63 Pages) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
High-Z
The High-Z instruction places all LLDRAM II outputs into a High-Z state, and causes the bypass register to be connected between
TDI and TDO when the TAP Controller is in the Shift DR state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the
values held in the Boundary Scan Register. Additionally, it causes the bypass register to be connected between TDI and TDO
when the TAP Controller is in the Shift DR state.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls is captured in the Boundary Scan Register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the LLDRAM II clock
operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results
may not be possible.
To ensure that the Boundary Scan Register will capture the correct value of a signal, the LLDRAM II signal must be stabilized long
enough to meet the TAP controller’s capture setup plus hold time (tCS + tCH). The LLDRAM II clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the value of the CK and CK captured in the Boundary Scan Register.
Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the Boundary
Scan Register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is
placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple
devices are connected together on a board.
Reserved for Future Use
The remaining instructions are not implemented but are reserved for future use. Do not use these instructions.
TAP Timing
T0
T1
T2
T3
T4
T5
Test Clock (TCK)
tTHTL
tTLTH
tTHTH
Test Mode Select (TMS)
tTHMX
tMVTH
Test Data-In (TDI)
tTHDX
tDVTH
Test Data-Out (TDO)
tTLOX
tTLOV
Rev: 1.04 11/2013
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Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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