GS4576C36GL-25I Datasheet, PDF (20/63 Pages) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
Write
Write data transfers are launched with a Write command, as shown below. A valid address must be provided during the Write
command.
During Write data transfers, each beat of incoming data is registered on crossings of DK and DK until the burst transfer is
complete. Write Latency (WL) that is always one cycle longer than the programmed Read Latency (RL), so the first valid data
registered at the first True crossing of the DK clocks WL cycles after the Write command.
A Write burst may be followed by a Read command (assuming tRC is met). At least one NOP command is required between Write
and Read commands to avoid data bus contention. The Write-to-Read timing diagrams illustrate the timing requirements for a
Write followed by a Read. Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. Input
data may be masked a High on an associated DM pin. The setup and hold times for the DM signal are tDS and tDH.W
Write Command
CK
CK
CS
WE
REF
Addr
A
BA(2:0)
BA
Rev: 1.04 11/2013
20/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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