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GS4576C36GL-25I Datasheet, PDF (47/63 Pages) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II) | |||
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GS4576C09/18/36L
AC Electrical Characteristics
Parameter
Symbol
â18
Min
Max
Clock
Input Clock Cycle Time
tCK
1.875
5.7
Input data clock cycle time
tDK
tCK
Clock jitter: period
tJITPER
â100
100
Clock jitter: cycle-to-cycle
tJITCC
â
200
Clock High Time
tCKH
tDKH
0.45
0.55
Clock Low Time
tCKL
tDKL
0.45
0.55
Clock to input data clock
tCKDK
â0.3
0.3
Mode register set cycle time
to any command
tMRSC
6
â
Setup Times
Address/command and input
setup time
tAS/tCS
0.3
â
Dataâin and data mask to
DK set up time
tDS
0.17
â
Hold Times
Address/command and input
hold time
tAH/tCS
0.3
â
Data-in and data mask to
DK setup time
tDH
0.17
â
Data and Data Strobe
Output data clock High time tQKH
0.9
1.1
Output data clock Low time tQKL
0.9
1.1
Halfâclock period
tQHP
MIN
(tQKH, tQKL)
â
QK edge to clock edge skew tCKQK
â0.2
0.2
QK edge to output data
edge
tQKQ0,
tQKQ1
â0.12
0.12
QK edge to any output data
edge
tQKQ
â0.22
0.22
QK edge to QVLD
tQKVLD
â0.22
0.22
Data Valid Window
tDVW
tDVW (MIN)
â
â24
Min
Max
2.5
5.7
tCK
â150
150
â
300
0.45
0.55
0.45
0.55
â0.45
0.5
6
â
0.4
â
0.25
â
0.4
â
0.25
â
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
â
â0.25
0.25
â0.2
0.2
â0.3
0.3
â0.3
0.3
tDVW (MIN)
â
â25
Min
Max
2.5
5.7
tCK
â150
150
â
300
0.45
0.55
0.45
0.55
â0.45
0.5
6
â
0.4
â
0.25
â
0.4
â
0.25
â
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
â
â0.25
0.25
â0.2
0.2
â0.3
0.3
â0.3
0.3
tDVW (MIN)
â
â33
Min
Max
3.3
5.7
tCK
â200
200
â
400
0.45
0.55
0.45
0.55
â0.45
1.2
6
â
0.5
â
0.3
â
0.5
â
0.3
â
0.9
1.1
0.9
1.1
MIN
(tQKH, tQKL)
â
â0.3
0.3
â0.25
0.25
â0.35
0.35
â0.35
0.35
tDVW (MIN)
â
ns â
ns â
ps 5, 6
ps â
tCK â
tCK â
ns â
tCK â
ns â
ns â
ns â
ns â
tCKH â
tCKL â
ââ
ns â
ns 7
ns 8
ns â
â9
Rev: 1.04 11/2013
47/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
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