GS4576C36GL-25I Datasheet, PDF (54/63 Pages) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II)

GS4576C09/18/36L
Boundary Scan Register
The Boundary Scan Register is connected to all the input and bidirectional balls on the LLDRAM II. Several bits are also included
in the scan register for reserved balls. The LLDRAM II has a 113-bit register.
The Boundary Scan Register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state.
The Boundary Scan Register table shows the order in which the bits are connected. Each bit corresponds to one of the balls on the
LLDRAM II package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE command is loaded in
the instruction register. The IDCODE is hardwired into the LLDRAM II and can be shifted out when the TAP controller is in the
shift-DR state. The ID register has a vendor code and other information described in the table below.
Identification Register Definitions
Instruction Field
Revision number (31:28)
Bit Size
abcd
Device ID (27:12)
GSI JEDEC ID code (11:1)
ID register presence indicator (0)
00jkidef10100111
01011011001
1
Bit Size
ab = die revision
cd = 00 for x9, 01 for x18, 10 for x36
def = 000 for 288Mb, 001 for 576Mb
i = 0 for common I/O, 1 for separate I/O
jk = 01 for LLDRAM II
Allows unique identification of LLDRAM II vendor
Indicates the presence of an ID register
TAP Instruction Set
Overview
Many different instructions (256) are possible with the 8-bit instruction register. All combinations used are listed in the Instruction
Codes table. These six instructions are described in detail below. The remaining instructions are reserved and should not be used.
The TAP controller used in this LLDRAM II is fully compliant to the 1149.1 convention.
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary Scan Register cells at output
balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using
the EXTEST instruction will be shifted into the Boundary Scan Register using the PRELOAD instruction. Thus, during the
Update-IR state of EXTEST, the output driver is turned on, and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the
TAP controller is given a test logic reset state.
Rev: 1.04 11/2013
54/62
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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