GS4576C36GL-25I Datasheet, PDF(30/63 Page) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II)

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GS4576C36GL-25I Datasheet, PDF (30/63 Pages) GSI Technology – 576Mb CIO Low Latency DRAM (LLDRAM II)

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GS4576C09/18/36L

MRS Command In Multiplexed Mode

The Mode Register Set command stores the data for controlling the RAM into the Mode Register. The register allows the user to

modify Read and Write pipeline length, burst length, test mode, and I/O options. The Multiplexed MRS command requires two

cycles to complete The Ax address is sampled on the true crossing of clock with the MRS Command. The Ay address and a

required NOP command are captured on the next next crossing of clock. After issuing a valid MRS command, tMRSC must be met

before any READ, WRITE, MRS, or AREF command can be issued to the LLDRAM II. This statement does not apply to the

consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be

issued when all banks are idle and no bursts are in progress.

Note: The data written by the prior burst length is not guaranteed to be accurate when the burst length of the device is changed.

MRS Command in Multiplexed Mode

MRS

REF

A(20:0)

BA(2:0)

Notes:

1. Recommended that all address pins held Low during dummy MRS commands.

2. A10âA18 must be Low.

3. Set address A5 High. This enbles the part to enter Multiplexed Address mode when in Non-Multiplexed mode operation. Multiplexed

Address mode can also be entered at some later time by issuing an MRS command with A5 High. Once address Bit A5 is set High, tMRSC

must be satisfied before the two-cycle multiplexed mode MRS command is issued.

4. Address A5 must be set High. This and the following step set the desired mode register once the LLDRAM II is in Multiplexed Address

mode.

5. Any command or address.

6. The above sequence must be followed in order to power up the LLDRAM II in the Multiplexed Address mode.

7. DLL must be reset if tCK or VDD are changed.

8. CK and CK must separated at all times to prevent bogus commands from being issued.

9. The sequence of the eight AUTO REFRESH commands (with respect to the 1024 NOP commands) does not matter. As is required for any

operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the same bank.

Rev: 1.04 11/2013

30/62

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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