English
Language : 

GX4002 Datasheet, PDF (64/74 Pages) Gennum Corporation – Dynamic on-chip power management control
◁
Table 7-1: Configuration and Status Register Map (Continued)
Register Name
CH0PLL_REG5
Register
Addressd
14
Parameter Name
CH0PLLPOLINV
CH0PLLBYPASS
CH0PLLAUTOBYPASSEN
CH0PLLRATESEL
Bit
Position
0:0
1:1
2:2
Access
RW
RW
RW
3:3
RW
RSVD
RSVD
RSVD
CH0PLL_REG9
CH0PLL_REG10
CH1PLL_REG1
CH1PLL_REG2
CH1PLL_REG3
RSVD
CH1PLL_REG5
CH0PLLRATESELVAL
RSVD
15
RSVD
16
RSVD
17
RSVD
RSVD
18
CH0PLLBWMULT
CH0PLLLOS
19
CH0PLLLOL
RSVD
CH1PLLLBWCURVT
20
RSVD
CH1PLLLBWCURVBE
21
RSVD
RSVD
22
CH1PLLCUR
RSVD
23
RSVD
CH1PLLPOLINV
CH1PLLBYPASS
CH1PLLAUTOBYPASSEN
24
CH1PLLRATESEL
4:4
RW
7:5
RW
7:0
RW
7:0
RW
7:0
RW
5:0
RW
7:6
RW
0:0
RO
1:1
RO
7:2
RW
4:0
RW
7:5
RW
4:0
RW
7:5
RW
1:0
RW
3:2
RW
7:4
RW
7:0
RW
0:0
RW
1:1
RW
2:2
RW
3:3
RW
CH1PLLRATESELVAL
4:4
RW
RSVD
7:5
RW
RSVD
25
RSVD
7:0
RW
RSVD
26
RSVD
7:0
RW
RSVD
27
RSVD
7:0
RW
NOTE: * Indicates bits for lower data rates (below 10G operation)
Reset Valueb
0
0
1
1
1
000
00001010
00100000
00000101
000000
10
0
0
000000
10011
000
01110
000
01
01
0000
00100000
0
0
1
1
1
000
00001010
00100000
00000101
Valid
Ranged
Function
0-1
0-1
0-1
0-1
0-1
0-7
0-255
0-255
0-255
0-63
0-3
0-1
0-1
0-63
0-31
0-7
0-31
0-7
0-3
0-3
0-15
0-255
0-1
0-1
0-1
0-1
0-1
0-7
0-255
0-255
0-255
When HIGH, inverts data path polarity.
When HIGH, forces CDR into bypass mode.
When HIGH, enables automatic bypass mode.
Selects data rates:
0 = 1.25 - 8.5G, 1= 10.3G or 14.025G
When HIGH, CH0PLLRATESEL is valid, otherwise
it is ignored.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
LBW multiplier:
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
Loss of signal when HIGH.
Loss of lock when HIGH.
Reserved. Do not change.
Adjusts LBW positive temperature coefficient
control.
Reserved. Do not change.
Adjusts LBW negative temperature coefficient
control.
Reserved. Do not change.
Reserved. Do not change.
Ch1 PLL control current.
Reserved. Do not change.
Reserved. Do not change.
When HIGH, inverts data path polarity.
When HIGH, forces CDR into bypass mode.
When HIGH, enables automatic bypass mode.
Selects data rates:
0 = 1.25 - 8.5G, 1 = 10.3G or 14.025G
When HIGH, CH1PLLRATESEL is valid.
Otherwise, it is ignored.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
Reserved. Do not change.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
64 of 74
Proprietary & Confidential
 ▷