GX4002 Datasheet, PDF (18/74 Pages) Gennum Corporation – Dynamic on-chip power management control

3.2.2 Ch0 PLL Variable Loop Bandwidth
The loop bandwidth of the channel 0 Phase Locked Loop (PLL) can be varied through the
digital control interface. The loop bandwidths are individually controlled, and can cover
the range of 1MHz to 23MHz through following five-bit registers (recommended settings
are shown):
Register Name
CH0PLL_REG1
CH0PLL_REG2
CH0PLL_REG9
Register
Address^d
10
11
18
Parameter Name
CH0PLLLBWCURVT
CH0PLLLBWCURVBE
CH0PLLLBWMULT
Bit
Position
Access
4:0
RW
4:0
RW
1:0
RW
Reset Value^b
10011
01110
10
Valid
Range^d
Function
0-31
Adjusts LBW positive temperature
coefficient control.
0-31
Adjusts LBW negative temperature
coefficient control.
0-3
LBW multiplier;
00 = 0.67, 10 = 1, 01 = 1.33, 11 = 1.67
The temperature coefficient of the loop bandwidth can be adjusted by weighted
summation of CH0PLLLBWCURVT, which has a positive temperature coefficient and
CH0PLLLBWCURVBE, which has a negative temperature coefficient. The default reset
values of the registers above produce an approximate loop bandwidth of 7MHz.
Table 3-3: Typical Loop Bandwidths for Various Register Settings
CH0PLLLBWMULT CH0PLLLBWCURVT CH0PLLLBWCURVBE
00
10 (default)
01
10
11
10011
10011
10011
11111
11000
01110
01110
01110
10110
11000
Loop
Bandwidth
4.6MHz
7.3MHz
9.9MHz
13MHz
22.7MHz
3.2.3 Channel 0 Output Polarity Invert
The channel 0 output polarity can be inverted through the following register:
Register Name
CH0PLL_REG5
Register
Address^d
14
Parameter Name
CH0PLLPOLINV
Bit
Position
Access
0:0
RW
Reset Value^b
0
Valid
Range^d
Function
0-1
When HIGH, inverts the Ch0 data path
polarity.
GX4002 2x2 14.025Gb/s Crosspoint Switch with Trace
Equalization and Output De-Emphasis
Data Sheet
55972 - 0
March 2012
18 of 74
Proprietary & Confidential